riscv/rocket-chip
1
0
Fork 0
Code Releases Activity

%s/master/manager/g

Browse Source
This commit is contained in:
Henry Cook 2014-12-29 22:56:18 -08:00
parent 77e5e6b561
commit 1cb65d5ec1
2 changed files with 2 additions and 2 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
rocket/src/main/scala/icache.scala
View File

@ -253,7 +253,7 @@ class ICache extends FrontendModule
val ack_q = Module(new Queue(new LogicalNetworkIO(new Finish), 1))
ack_q.io.enq.valid := refill_done && co.requiresAckForGrant(refill_bits.payload)
ack_q.io.enq.bits.payload.master_xact_id := refill_bits.payload.master_xact_id
ack_q.io.enq.bits.payload.manager_xact_id := refill_bits.payload.manager_xact_id
ack_q.io.enq.bits.header.dst := refill_bits.header.src
// output signals

2
rocket/src/main/scala/nbdcache.scala
View File

@ -260,7 +260,7 @@ class MSHR(id: Int) extends L1HellaCacheModule {
val ackq = Module(new Queue(new LogicalNetworkIO(new Finish), 1))
ackq.io.enq.valid := (wb_done || refill_done) && co.requiresAckForGrant(io.mem_grant.bits.payload)
ackq.io.enq.bits.payload.master_xact_id := io.mem_grant.bits.payload.master_xact_id
ackq.io.enq.bits.payload.manager_xact_id := io.mem_grant.bits.payload.manager_xact_id
ackq.io.enq.bits.header.dst := io.mem_grant.bits.header.src
val can_finish = state === s_invalid || state === s_refill_req || state === s_refill_resp
io.mem_finish.valid := ackq.io.deq.valid && can_finish