Removed sret from ptw; sret now comes thru io.cpu to dcache

rocket/src/main/scala/ctrl.scala

@@ -675,6 +675,7 @@ class Control extends CoreModule
   io.dmem.req.bits.cmd  := ex_ctrl.mem_cmd
   io.dmem.req.bits.typ  := ex_ctrl.mem_type
   io.dmem.req.bits.phys := Bool(false)
+  io.dmem.sret          := io.dpath.sret
 
   io.rocc.cmd.valid := wb_rocc_val
   io.rocc.exception := wb_reg_xcpt && sr.er

rocket/src/main/scala/dpath.scala

@@ -177,7 +177,6 @@ class Datapath extends CoreModule
 
   io.ptw.ptbr := pcr.io.ptbr
   io.ptw.invalidate := pcr.io.fatc
-  io.ptw.sret := io.ctrl.sret
   io.ptw.status := pcr.io.status
 
   // memory stage

rocket/src/main/scala/nbdcache.scala

@@ -83,6 +83,7 @@ class HellaCacheIO extends CoreBundle {
   val resp = Valid(new HellaCacheResp).flip
   val replay_next = Valid(Bits(width = coreDCacheReqTagBits)).flip
   val xcpt = (new HellaCacheExceptions).asInput
+  val sret = Bool(OUTPUT)
   val ordered = Bool(INPUT)
 }
 
@@ -750,7 +751,7 @@ class HellaCache extends L1HellaCacheModule {
       lrsc_count := 0
     }
   }
-  when (io.ptw.sret) { lrsc_count := 0 }
+  when (io.cpu.sret) { lrsc_count := 0 }
 
   val s2_data = Vec.fill(nWays){Bits(width = encRowBits)}
   for (w <- 0 until nWays) {

rocket/src/main/scala/ptw.scala

@@ -17,13 +17,11 @@ class TLBPTWIO extends CoreBundle {
   val resp = Valid(new PTWResp).flip
   val status = new Status().asInput
   val invalidate = Bool(INPUT)
-  val sret = Bool(INPUT)
 }
 
 class DatapathPTWIO extends CoreBundle {
   val ptbr = UInt(INPUT, paddrBits)
   val invalidate = Bool(INPUT)
-  val sret = Bool(INPUT)
   val status = new Status().asInput
 }
 
@@ -83,7 +81,6 @@ class PTW(n: Int) extends CoreModule
     io.requestor(i).resp.bits.perm := r_pte(8,3)
     io.requestor(i).resp.bits.ppn := resp_ppn.toUInt
     io.requestor(i).invalidate := io.dpath.invalidate
-    io.requestor(i).sret := io.dpath.sret
     io.requestor(i).status := io.dpath.status
   }