add l2 dmem signal to rocc
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72ea24283b
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@ -43,6 +43,7 @@ class RoCCInterface extends Bundle
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// These should be handled differently, eventually
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val imem = new UncachedTileLinkIO
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val dmem = new TileLinkIO
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val iptw = new TLBPTWIO
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val dptw = new TLBPTWIO
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val pptw = new TLBPTWIO
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@ -124,6 +125,11 @@ class AccumulatorExample extends RoCC
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io.imem.acquire.valid := false
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io.imem.grant.ready := false
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io.imem.finish.valid := false
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io.dmem.acquire.valid := false
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io.dmem.release.valid := false
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io.dmem.finish.valid := false
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io.dmem.probe.ready := false
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io.dmem.grant.ready := false
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io.iptw.req.valid := false
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io.dptw.req.valid := false
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io.pptw.req.valid := false
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@ -38,10 +38,10 @@ class RocketTile(resetSignal: Bool = null) extends Tile(resetSignal) {
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core.io.imem <> icache.io.cpu
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core.io.ptw <> ptw.io.dpath
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val memArb = Module(new UncachedTileLinkIOArbiterThatAppendsArbiterId(params(NTilePorts)))
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val dcPortId = 0
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memArb.io.in(dcPortId) <> dcache.io.mem
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memArb.io.in(1) <> icache.io.mem
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val memArb = Module(new TileLinkIOArbiterThatAppendsArbiterId(params(NTilePorts)))
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io.tilelink <> memArb.io.out
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memArb.io.in(0) <> dcache.io.mem
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memArb.io.in(1) <> TileLinkIOWrapper(icache.io.mem)
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//If so specified, build an RoCC module and wire it in
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params(BuildRoCC)
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@ -51,21 +51,10 @@ class RocketTile(resetSignal: Bool = null) extends Tile(resetSignal) {
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core.io.rocc <> rocc.io
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dcIF.io.requestor <> rocc.io.mem
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dcArb.io.requestor(2) <> dcIF.io.cache
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memArb.io.in(2) <> rocc.io.imem
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memArb.io.in(2) <> TileLinkIOWrapper(rocc.io.imem)
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memArb.io.in(3) <> rocc.io.dmem
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ptw.io.requestor(2) <> rocc.io.iptw
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ptw.io.requestor(3) <> rocc.io.dptw
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ptw.io.requestor(4) <> rocc.io.pptw
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}
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io.tilelink.acquire <> memArb.io.out.acquire
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io.tilelink.grant <> memArb.io.out.grant
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io.tilelink.finish <> memArb.io.out.finish
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// Probes and releases routed directly to coherent dcache
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io.tilelink.probe <> dcache.io.mem.probe
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// Mimic client id extension done by UncachedTileLinkIOArbiter for Acquires from either client)
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io.tilelink.release.valid := dcache.io.mem.release.valid
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dcache.io.mem.release.ready := io.tilelink.release.ready
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io.tilelink.release.bits := dcache.io.mem.release.bits
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io.tilelink.release.bits.payload.client_xact_id := Cat(dcache.io.mem.release.bits.payload.client_xact_id, UInt(dcPortId, log2Up(params(NTilePorts))))
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}
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