Major tilelink revision for uncached message types
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@ -258,14 +258,14 @@ class ICache extends FrontendModule
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io.resp.bits.datablock := Mux1H(s2_tag_hit, s2_dout)
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val ack_q = Module(new Queue(new LogicalNetworkIO(new Finish), 1))
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ack_q.io.enq.valid := refill_done && co.requiresAckForGrant(refill_bits.payload.g_type)
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ack_q.io.enq.valid := refill_done && co.requiresAckForGrant(refill_bits.payload)
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ack_q.io.enq.bits.payload.master_xact_id := refill_bits.payload.master_xact_id
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ack_q.io.enq.bits.header.dst := refill_bits.header.src
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// output signals
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io.resp.valid := s2_hit
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io.mem.acquire.valid := (state === s_request) && ack_q.io.enq.ready
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io.mem.acquire.bits.payload := Acquire(co.getUncachedReadAcquireType, s2_addr >> UInt(blockOffBits), UInt(0))
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io.mem.acquire.bits.payload := UncachedRead(s2_addr >> UInt(blockOffBits))
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io.mem.finish <> ack_q.io.deq
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// control state machine
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@ -254,7 +254,7 @@ class MSHR(id: Int) extends L1HellaCacheModule {
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}
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val ackq = Module(new Queue(new LogicalNetworkIO(new Finish), 1))
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ackq.io.enq.valid := (wb_done || refill_done) && co.requiresAckForGrant(io.mem_grant.bits.payload.g_type)
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ackq.io.enq.valid := (wb_done || refill_done) && co.requiresAckForGrant(io.mem_grant.bits.payload)
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ackq.io.enq.bits.payload.master_xact_id := io.mem_grant.bits.payload.master_xact_id
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ackq.io.enq.bits.header.dst := io.mem_grant.bits.header.src
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val can_finish = state === s_invalid || state === s_refill_req || state === s_refill_resp
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@ -288,9 +288,7 @@ class MSHR(id: Int) extends L1HellaCacheModule {
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io.wb_req.bits.r_type := co.getReleaseTypeOnVoluntaryWriteback()
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io.mem_req.valid := state === s_refill_req && ackq.io.enq.ready
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io.mem_req.bits.a_type := acquire_type
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io.mem_req.bits.addr := Cat(io.tag, req_idx).toUInt
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io.mem_req.bits.client_xact_id := Bits(id)
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io.mem_req.bits := Acquire(acquire_type, Cat(io.tag, req_idx).toUInt, Bits(id))
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io.mem_finish <> ackq.io.deq
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io.meta_read.valid := state === s_drain_rpq
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