Fixed BHT update error.
- separated out BTB/BHT update - BHT updates counters on every branch - BTB update only on mispredicted and taken branches
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@ -51,7 +51,7 @@ class BHTResp extends Bundle with BTBParameters {
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// - updated speculatively in fetch (if there's a BTB hit).
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// - on a mispredict, the history register is reset (again, only if BTB hit).
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// The counter table:
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// - each counter corresponds with the "fetch pc" (not the PC of the branch).
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// - each counter corresponds with the address of the fetch packet ("fetch pc").
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// - updated when a branch resolves (and BTB was a hit for that branch).
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// The updating branch must provide its "fetch pc".
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class BHT(nbht: Int) {
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@ -65,10 +65,10 @@ class BHT(nbht: Int) {
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when (update) { history := Cat(taken, history(nbhtbits-1,1)) }
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res
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}
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def update(addr: UInt, d: BHTResp, taken: Bool): Unit = {
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def update(addr: UInt, d: BHTResp, taken: Bool, mispredict: Bool): Unit = {
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val index = addr(nbhtbits+1,2) ^ d.history
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table(index) := Cat(taken, (d.value(1) & d.value(0)) | ((d.value(1) | d.value(0)) & taken))
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history := Cat(taken, d.history(nbhtbits-1,1))
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when (mispredict) { history := Cat(taken, d.history(nbhtbits-1,1)) }
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}
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private val table = Mem(UInt(width = 2), nbht)
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@ -88,6 +88,15 @@ class BTBUpdate extends Bundle with BTBParameters {
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val br_pc = UInt(width = vaddrBits)
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}
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// BHT update occurs during branch resolution on all conditional branches.
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// - "pc" is what future fetch PCs will tag match against.
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class BHTUpdate extends Bundle with BTBParameters {
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val prediction = Valid(new BTBResp)
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val pc = UInt(width = vaddrBits)
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val taken = Bool()
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val mispredict = Bool()
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}
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class RASUpdate extends Bundle with BTBParameters {
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val isCall = Bool()
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val isReturn = Bool()
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@ -96,9 +105,9 @@ class RASUpdate extends Bundle with BTBParameters {
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}
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// - "bridx" is the low-order PC bits of the predicted branch (after
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// shifting off the lowest log(inst_bytes) bits off).
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// shifting off the lowest log(inst_bytes) bits off).
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// - "resp.mask" provides a mask of valid instructions (instructions are
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// masked off by the predicted taken branch).
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// masked off by the predicted taken branch).
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class BTBResp extends Bundle with BTBParameters {
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val taken = Bool()
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val mask = Bits(width = params(FetchWidth))
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@ -120,7 +129,8 @@ class BTB(updates_out_of_order: Boolean = false) extends Module with BTBParamete
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val io = new Bundle {
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val req = Valid(new BTBReq).flip
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val resp = Valid(new BTBResp)
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val update = Valid(new BTBUpdate).flip
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val btb_update = Valid(new BTBUpdate).flip
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val bht_update = Valid(new BHTUpdate).flip
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val ras_update = Valid(new RASUpdate).flip
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val invalidate = Bool(INPUT)
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}
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@ -151,67 +161,62 @@ class BTB(updates_out_of_order: Boolean = false) extends Module with BTBParamete
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idxValid & idxMatch & idxPageMatch
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}
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val r_update = Pipe(io.update)
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val r_btb_update = Pipe(io.btb_update)
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val update_target = io.req.bits.addr
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val pageHit = pageMatch(io.req.bits.addr)
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val hits = tagMatch(io.req.bits.addr, pageHit)
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val updatePageHit = pageMatch(r_update.bits.pc)
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val updateHits = tagMatch(r_update.bits.pc, updatePageHit)
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val updatePageHit = pageMatch(r_btb_update.bits.pc)
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val updateHits = tagMatch(r_btb_update.bits.pc, updatePageHit)
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private var lfsr = LFSR16(r_update.valid)
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private var lfsr = LFSR16(r_btb_update.valid)
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def rand(width: Int) = {
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lfsr = lfsr(lfsr.getWidth-1,1)
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Random.oneHot(width, lfsr)
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}
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val updateHit = r_update.bits.prediction.valid
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val updateTarget = r_update.bits.taken
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val updateHit = r_btb_update.bits.prediction.valid
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val useUpdatePageHit = updatePageHit.orR
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val doIdxPageRepl = updateTarget && !useUpdatePageHit
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val doIdxPageRepl = !useUpdatePageHit
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val idxPageRepl = UInt()
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val idxPageUpdateOH = Mux(useUpdatePageHit, updatePageHit, idxPageRepl)
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val idxPageUpdate = OHToUInt(idxPageUpdateOH)
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val idxPageReplEn = Mux(doIdxPageRepl, idxPageRepl, UInt(0))
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val samePage = page(r_update.bits.pc) === page(update_target)
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val samePage = page(r_btb_update.bits.pc) === page(update_target)
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val usePageHit = (pageHit & ~idxPageReplEn).orR
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val doTgtPageRepl = updateTarget && !samePage && !usePageHit
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val doTgtPageRepl = !samePage && !usePageHit
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val tgtPageRepl = Mux(samePage, idxPageUpdateOH, idxPageUpdateOH(nPages-2,0) << 1 | idxPageUpdateOH(nPages-1))
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val tgtPageUpdate = OHToUInt(Mux(usePageHit, pageHit, tgtPageRepl))
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val tgtPageReplEn = Mux(doTgtPageRepl, tgtPageRepl, UInt(0))
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val doPageRepl = doIdxPageRepl || doTgtPageRepl
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val pageReplEn = idxPageReplEn | tgtPageReplEn
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idxPageRepl := UIntToOH(Counter(r_update.valid && doPageRepl, nPages)._1)
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idxPageRepl := UIntToOH(Counter(r_btb_update.valid && doPageRepl, nPages)._1)
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when (r_update.valid && updateTarget) {
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assert(io.req.bits.addr === r_update.bits.target, "BTB request != I$ target")
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when (r_btb_update.valid) {
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assert(io.req.bits.addr === r_btb_update.bits.target, "BTB request != I$ target")
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val nextRepl = Counter(!updateHit, entries)._1
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var waddr:UInt = null
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if (!updates_out_of_order) {
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waddr = Mux(updateHit, r_update.bits.prediction.bits.entry, nextRepl)
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} else {
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println(" BTB accepts out-of-order updates.")
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waddr = Mux(updateHits.orR, OHToUInt(updateHits), nextRepl)
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}
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val waddr =
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if (updates_out_of_order) Mux(updateHits.orR, OHToUInt(updateHits), nextRepl)
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else Mux(updateHit, r_btb_update.bits.prediction.bits.entry, nextRepl)
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// invalidate entries if we stomp on pages they depend upon
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idxValid := idxValid & ~Vec.tabulate(entries)(i => (pageReplEn & (idxPagesOH(i) | tgtPagesOH(i))).orR).toBits
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idxValid(waddr) := Bool(true)
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idxs(waddr) := r_update.bits.pc
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idxValid(waddr) := Bool(true)
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idxs(waddr) := r_btb_update.bits.pc
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tgts(waddr) := update_target
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idxPages(waddr) := idxPageUpdate
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tgtPages(waddr) := tgtPageUpdate
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useRAS(waddr) := r_update.bits.isReturn
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isJump(waddr) := r_update.bits.isJump
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useRAS(waddr) := r_btb_update.bits.isReturn
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isJump(waddr) := r_btb_update.bits.isJump
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if (params(FetchWidth) == 1) {
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brIdx(waddr) := UInt(0)
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} else {
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brIdx(waddr) := r_update.bits.br_pc >> log2Up(params(CoreInstBits)/8)
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brIdx(waddr) := r_btb_update.bits.br_pc >> log2Up(params(CoreInstBits)/8)
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}
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require(nPages % 2 == 0)
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@ -222,9 +227,9 @@ class BTB(updates_out_of_order: Boolean = false) extends Module with BTBParamete
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when (en && pageReplEn(i)) { pages(i) := data }
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writeBank(0, 2, Mux(idxWritesEven, doIdxPageRepl, doTgtPageRepl),
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Mux(idxWritesEven, page(r_update.bits.pc), page(update_target)))
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Mux(idxWritesEven, page(r_btb_update.bits.pc), page(update_target)))
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writeBank(1, 2, Mux(idxWritesEven, doTgtPageRepl, doIdxPageRepl),
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Mux(idxWritesEven, page(update_target), page(r_update.bits.pc)))
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Mux(idxWritesEven, page(update_target), page(r_btb_update.bits.pc)))
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when (doPageRepl) { pageValid := pageValid | pageReplEn }
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}
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@ -243,17 +248,16 @@ class BTB(updates_out_of_order: Boolean = false) extends Module with BTBParamete
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io.resp.bits.mask := UInt(1)
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} else {
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// note: btb_resp is clock gated, so the mask is only relevant for the io.resp.valid case
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val all_ones = UInt((1 << (params(FetchWidth)+1))-1)
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io.resp.bits.mask := Mux(io.resp.bits.taken, Cat((UInt(1) << brIdx(io.resp.bits.entry))-1, UInt(1)),
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all_ones)
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SInt(-1))
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}
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if (nBHT > 0) {
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val bht = new BHT(nBHT)
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val res = bht.get(io.req.bits.addr, io.req.valid && hits.orR && !Mux1H(hits, isJump))
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val update_btb_hit = io.update.bits.prediction.valid
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when (io.update.valid && update_btb_hit && !io.update.bits.isJump) {
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bht.update(io.update.bits.pc, io.update.bits.prediction.bits.bht, io.update.bits.taken)
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val update_btb_hit = io.bht_update.bits.prediction.valid
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when (io.bht_update.valid && update_btb_hit) {
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bht.update(io.bht_update.bits.pc, io.bht_update.bits.prediction.bits.bht, io.bht_update.bits.taken, io.bht_update.bits.mispredict)
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}
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when (!res.value(0) && !Mux1H(hits, isJump)) { io.resp.bits.taken := false }
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io.resp.bits.bht := res
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@ -652,17 +652,24 @@ class Control extends Module
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Mux(replay_wb, PC_WB, // replay
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PC_MEM)))
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io.imem.btb_update.valid := take_pc_mem && !take_pc_wb
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io.imem.btb_update.valid := io.dpath.mem_misprediction && ((mem_reg_branch && io.dpath.mem_br_taken) || mem_reg_jalr || mem_reg_jal) && !take_pc_wb
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io.imem.btb_update.bits.prediction.valid := mem_reg_btb_hit
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io.imem.btb_update.bits.prediction.bits := mem_reg_btb_resp
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io.imem.btb_update.bits.taken := mem_reg_branch && io.dpath.mem_br_taken || io.imem.btb_update.bits.isJump
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io.imem.btb_update.bits.isJump := mem_reg_jal || mem_reg_jalr
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io.imem.btb_update.bits.isReturn := mem_reg_jalr && io.dpath.mem_rs1_ra
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io.imem.bht_update.valid := mem_reg_branch && !take_pc_wb
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io.imem.bht_update.bits.taken := io.dpath.mem_br_taken
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io.imem.bht_update.bits.mispredict := io.dpath.mem_misprediction
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io.imem.bht_update.bits.prediction.valid := mem_reg_btb_hit
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io.imem.bht_update.bits.prediction.bits := mem_reg_btb_resp
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io.imem.ras_update.valid := io.imem.btb_update.bits.isJump && !take_pc_wb
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io.imem.ras_update.bits.isCall := mem_reg_wen && io.dpath.mem_waddr(0)
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io.imem.ras_update.bits.isReturn := mem_reg_jalr && io.dpath.mem_rs1_ra
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io.imem.ras_update.bits.prediction.valid := mem_reg_btb_hit
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io.imem.ras_update.bits.prediction.bits := mem_reg_btb_resp
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io.imem.req.valid := take_pc
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val bypassDst = Array(id_raddr1, id_raddr2)
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@ -287,6 +287,7 @@ class Datapath extends Module
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io.imem.btb_update.bits.pc := mem_reg_pc
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io.imem.btb_update.bits.target := io.imem.req.bits.pc
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io.imem.btb_update.bits.br_pc := mem_reg_pc
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io.imem.bht_update.bits.pc := mem_reg_pc
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io.imem.ras_update.bits.returnAddr := mem_int_wdata
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// for hazard/bypass opportunity detection
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@ -33,6 +33,7 @@ class CPUFrontendIO extends CoreBundle {
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val resp = Decoupled(new FrontendResp).flip
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val btb_resp = Valid(new BTBResp).flip
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val btb_update = Valid(new BTBUpdate)
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val bht_update = Valid(new BHTUpdate)
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val ras_update = Valid(new RASUpdate)
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val ptw = new TLBPTWIO().flip
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val invalidate = Bool(OUTPUT)
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@ -88,7 +89,8 @@ class Frontend(btb_updates_out_of_order: Boolean = false) extends FrontendModule
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btb.io.req.valid := !stall && !icmiss
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btb.io.req.bits.addr := s1_pc & SInt(-coreInstBytes)
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btb.io.update := io.cpu.btb_update
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btb.io.btb_update := io.cpu.btb_update
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btb.io.bht_update := io.cpu.bht_update
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btb.io.ras_update := io.cpu.ras_update
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btb.io.invalidate := io.cpu.invalidate || io.cpu.ptw.invalidate
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