More control cleanup
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2aee85cb11
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@ -31,7 +31,6 @@ class CtrlDpathIO extends Bundle
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val badvaddr_wen = Bool(OUTPUT) // high for a load/store access fault
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// inputs from datapath
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val inst = Bits(INPUT, 32)
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val jalr_eq = Bool(INPUT)
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val mem_br_taken = Bool(INPUT)
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val mem_misprediction = Bool(INPUT)
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val div_mul_rdy = Bool(INPUT)
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@ -371,7 +370,6 @@ class Control extends Module
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val wb_reg_xcpt = Reg(Bool())
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val wb_reg_replay = Reg(Bool())
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val wb_reg_cause = Reg(UInt())
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val wb_reg_fp_val = Reg(Bool())
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val take_pc_wb = Bool()
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val mem_misprediction = io.dpath.mem_misprediction && mem_reg_valid && (mem_ctrl.branch || mem_ctrl.jalr || mem_ctrl.jal)
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@ -444,21 +442,15 @@ class Control extends Module
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(id_ctrl.scall, UInt(Causes.syscall)),
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(id_ctrl.rocc && !io.dpath.status.er, UInt(Causes.accelerator_disabled))))
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ex_reg_valid := !ctrl_killd
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ex_reg_xcpt := !ctrl_killd && id_xcpt
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ex_reg_xcpt_interrupt := id_interrupt && !take_pc && io.imem.resp.valid
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when (id_xcpt) { ex_reg_cause := id_cause }
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when (ctrl_killd) {
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ex_reg_btb_hit := false
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ex_reg_valid := Bool(false)
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ex_reg_flush_pipe := Bool(false)
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ex_reg_load_use := Bool(false)
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ex_reg_xcpt := Bool(false)
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}
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.otherwise {
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when (!ctrl_killd) {
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ex_ctrl := id_ctrl
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ex_reg_btb_hit := io.imem.btb_resp.valid
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when (io.imem.btb_resp.valid) { ex_reg_btb_resp := io.imem.btb_resp.bits }
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ex_reg_valid := Bool(true)
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ex_reg_flush_pipe := id_ctrl.fence_i || id_csr_flush
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ex_reg_load_use := id_load_use
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ex_reg_xcpt := id_xcpt
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