Removed TLBPTWIO from the io.cpu bundle for icache/dcache

rocket/src/main/scala/icache.scala

@@ -37,7 +37,6 @@ class CPUFrontendIO extends Bundle {
   val btb_update = Valid(new BTBUpdate)
   val bht_update = Valid(new BHTUpdate)
   val ras_update = Valid(new RASUpdate)
-  val ptw = new TLBPTWIO().flip
   val invalidate = Bool(OUTPUT)
 }
 
@@ -45,6 +44,7 @@ class Frontend(btb_updates_out_of_order: Boolean = false) extends FrontendModule
 {
   val io = new Bundle {
     val cpu = new CPUFrontendIO().flip
+    val ptw = new TLBPTWIO()
     val mem = new UncachedTileLinkIO
   }
 
@@ -94,9 +94,9 @@ class Frontend(btb_updates_out_of_order: Boolean = false) extends FrontendModule
   btb.io.btb_update := io.cpu.btb_update
   btb.io.bht_update := io.cpu.bht_update
   btb.io.ras_update := io.cpu.ras_update
-  btb.io.invalidate := io.cpu.invalidate || io.cpu.ptw.invalidate
+  btb.io.invalidate := io.cpu.invalidate || io.ptw.invalidate
 
-  tlb.io.ptw <> io.cpu.ptw
+  tlb.io.ptw <> io.ptw
   tlb.io.req.valid := !stall && !icmiss
   tlb.io.req.bits.vpn := s1_pc >> UInt(pgIdxBits)
   tlb.io.req.bits.asid := UInt(0)
@@ -108,7 +108,7 @@ class Frontend(btb_updates_out_of_order: Boolean = false) extends FrontendModule
   icache.io.req.bits.idx := Mux(io.cpu.req.valid, io.cpu.req.bits.pc, npc)
   icache.io.invalidate := io.cpu.invalidate
   icache.io.req.bits.ppn := tlb.io.resp.ppn
-  icache.io.req.bits.kill := io.cpu.req.valid || tlb.io.resp.miss || icmiss || io.cpu.ptw.invalidate
+  icache.io.req.bits.kill := io.cpu.req.valid || tlb.io.resp.miss || icmiss || io.ptw.invalidate
   icache.io.resp.ready := !stall && !s1_same_block
 
   io.cpu.resp.valid := s2_valid && (s2_xcpt_if || icache.io.resp.valid)

rocket/src/main/scala/nbdcache.scala

@@ -83,7 +83,6 @@ class HellaCacheIO extends CoreBundle {
   val resp = Valid(new HellaCacheResp).flip
   val replay_next = Valid(Bits(width = coreDCacheReqTagBits)).flip
   val xcpt = (new HellaCacheExceptions).asInput
-  val ptw = new TLBPTWIO().flip
   val ordered = Bool(INPUT)
 }
 
@@ -596,6 +595,7 @@ class DataArray extends L1HellaCacheModule {
 class HellaCache extends L1HellaCacheModule {
   val io = new Bundle {
     val cpu = (new HellaCacheIO).flip
+    val ptw = new TLBPTWIO()
     val mem = new TileLinkIO
   }
  
@@ -634,7 +634,7 @@ class HellaCache extends L1HellaCacheModule {
   val s1_readwrite = s1_read || s1_write || isPrefetch(s1_req.cmd)
 
   val dtlb = Module(new TLB)
-  dtlb.io.ptw <> io.cpu.ptw
+  dtlb.io.ptw <> io.ptw
   dtlb.io.req.valid := s1_valid_masked && s1_readwrite && !s1_req.phys
   dtlb.io.req.bits.passthrough := s1_req.phys
   dtlb.io.req.bits.asid := UInt(0)
@@ -750,7 +750,7 @@ class HellaCache extends L1HellaCacheModule {
       lrsc_count := 0
     }
   }
-  when (io.cpu.ptw.sret) { lrsc_count := 0 }
+  when (io.ptw.sret) { lrsc_count := 0 }
 
   val s2_data = Vec.fill(nWays){Bits(width = encRowBits)}
   for (w <- 0 until nWays) {

rocket/src/main/scala/tile.scala

@@ -31,8 +31,8 @@ class RocketTile(resetSignal: Bool = null) extends Tile(resetSignal) {
   dcArb.io.requestor(1) <> core.io.dmem
   dcArb.io.mem <> dcache.io.cpu
 
-  ptw.io.requestor(0) <> icache.io.cpu.ptw
-  ptw.io.requestor(1) <> dcache.io.cpu.ptw
+  ptw.io.requestor(0) <> icache.io.ptw
+  ptw.io.requestor(1) <> dcache.io.ptw
 
   core.io.host <> io.host
   core.io.imem <> icache.io.cpu