riscv/rocket-chip
1
0
Fork 0
Code Releases Activity

Explicitely convert results of Bits Muxes to UInt

Browse Source 
Chisel updated to emit SInt result instead of UInt so this commit addresses this change.
This commit is contained in:
Stephen Twigg 2015-02-03 18:10:54 -08:00
parent 741e6b77ad
commit 3d35ccd401
1 changed files with 2 additions and 2 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
rocket/src/main/scala/dpath.scala
View File

@ -231,10 +231,10 @@ class Datapath extends CoreModule
val mem_br_target = mem_reg_pc +
Mux(io.ctrl.mem_ctrl.branch && io.ctrl.mem_br_taken, imm(IMM_SB, mem_reg_inst),
Mux(io.ctrl.mem_ctrl.jal, imm(IMM_UJ, mem_reg_inst), SInt(4)))
val mem_npc = Mux(io.ctrl.mem_ctrl.jalr, Cat(vaSign(mem_reg_wdata, mem_reg_wdata), mem_reg_wdata(vaddrBits-1,0)), mem_br_target)
val mem_npc = Mux(io.ctrl.mem_ctrl.jalr, Cat(vaSign(mem_reg_wdata, mem_reg_wdata), mem_reg_wdata(vaddrBits-1,0)), mem_br_target).toUInt
io.ctrl.mem_misprediction := mem_npc != ex_reg_pc || !io.ctrl.ex_valid
io.ctrl.mem_rs1_ra := mem_reg_inst(19,15) === 1
val mem_int_wdata = Mux(io.ctrl.mem_ctrl.jalr, mem_br_target, mem_reg_wdata)
val mem_int_wdata = Mux(io.ctrl.mem_ctrl.jalr, mem_br_target, mem_reg_wdata).toUInt
// writeback stage
when (!mem_reg_kill) {