riscv/rocket-chip
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uncached port should be a HeaderlessUncachedTileLinkIO type

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Yunsup Lee 2015-03-13 02:12:23 -07:00
parent 51e4cd7616
commit ebbd14254c
1 changed files with 1 additions and 1 deletions
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rocket/src/main/scala/tile.scala
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@ -14,7 +14,7 @@ case object BuildRoCC extends Field[Option[() => RoCC]]
abstract class Tile(resetSignal: Bool = null) extends Module(_reset = resetSignal) {
val io = new Bundle {
val cached = new HeaderlessTileLinkIO
val uncached = new HeaderlessTileLinkIO
val uncached = new HeaderlessUncachedTileLinkIO
val host = new HTIFIO
}
}