WritebackUnit multibeat control logic bugfix
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@ -418,7 +418,8 @@ class WritebackUnit extends L1HellaCacheModule {
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data_req_cnt := data_req_cnt - Mux[UInt](Bool(refillCycles > 1) && r1_data_req_fired, 2, 1)
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} .elsewhen(beat_done) { if(refillCyclesPerBeat > 1) buf_v := 0 }
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when(!r1_data_req_fired) {
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active := data_req_cnt < UInt(refillCycles)
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// We're done if this is the final data request and the Release can be sent
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active := data_req_cnt < UInt(refillCycles) || !io.release.ready
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}
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}
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}
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