sret bugfix: bypass arbiter
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@ -121,6 +121,7 @@ class AccumulatorExample extends RoCC
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io.mem.req.bits.cmd := M_XRD // perform a load (M_XWR for stores)
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io.mem.req.bits.typ := MT_D // D = 8 bytes, W = 4, H = 2, B = 1
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io.mem.req.bits.data := Bits(0) // we're not performing any stores...
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io.mem.sret := false
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io.imem.acquire.valid := false
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io.imem.grant.ready := false
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@ -26,6 +26,7 @@ class RocketTile(resetSignal: Bool = null) extends Tile(resetSignal) {
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val ptw = Module(new PTW(params(NPTWPorts)))
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val core = Module(new Core, { case CoreName => "Rocket" })
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dcache.io.cpu.sret := core.io.dmem.sret
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val dcArb = Module(new HellaCacheArbiter(params(NDCachePorts)))
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dcArb.io.requestor(0) <> ptw.io.mem
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dcArb.io.requestor(1) <> core.io.dmem
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