Merge branch 'ss-frontend'
This commit is contained in:
Andrew Waterman
commit
a98127c09e
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@ -45,6 +45,15 @@ class BHTResp extends Bundle with BTBParameters {
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val value = UInt(width = 2)
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}
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// BHT contains table of 2-bit counters and a global history register.
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// The BHT only predicts and updates when there is a BTB hit.
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// The global history:
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// - updated speculatively in fetch (if there's a BTB hit).
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// - on a mispredict, the history register is reset (again, only if BTB hit).
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// The counter table:
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// - each counter corresponds with the address of the fetch packet ("fetch pc").
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// - updated when a branch resolves (and BTB was a hit for that branch).
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// The updating branch must provide its "fetch pc".
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class BHT(nbht: Int) {
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val nbhtbits = log2Up(nbht)
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def get(addr: UInt, update: Bool): BHTResp = {
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@ -66,20 +75,43 @@ class BHT(nbht: Int) {
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val history = Reg(UInt(width = nbhtbits))
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}
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// BTB update occurs during branch resolution (and only on a mispredict).
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// - "pc" is what future fetch PCs will tag match against.
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// - "br_pc" is the PC of the branch instruction.
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class BTBUpdate extends Bundle with BTBParameters {
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val prediction = Valid(new BTBResp)
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val pc = UInt(width = vaddrBits)
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val target = UInt(width = vaddrBits)
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val returnAddr = UInt(width = vaddrBits)
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val taken = Bool()
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val isJump = Bool()
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val isCall = Bool()
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val isReturn = Bool()
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val br_pc = UInt(width = vaddrBits)
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}
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// BHT update occurs during branch resolution on all conditional branches.
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// - "pc" is what future fetch PCs will tag match against.
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class BHTUpdate extends Bundle with BTBParameters {
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val prediction = Valid(new BTBResp)
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val pc = UInt(width = vaddrBits)
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val taken = Bool()
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val mispredict = Bool()
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}
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class RASUpdate extends Bundle with BTBParameters {
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val isCall = Bool()
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val isReturn = Bool()
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val returnAddr = UInt(width = vaddrBits)
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val prediction = Valid(new BTBResp)
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}
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// - "bridx" is the low-order PC bits of the predicted branch (after
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// shifting off the lowest log(inst_bytes) bits off).
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// - "resp.mask" provides a mask of valid instructions (instructions are
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// masked off by the predicted taken branch).
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class BTBResp extends Bundle with BTBParameters {
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val taken = Bool()
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val mask = Bits(width = params(FetchWidth))
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val bridx = Bits(width = log2Up(params(FetchWidth)))
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val target = UInt(width = vaddrBits)
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val entry = UInt(width = opaqueBits)
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val bht = new BHTResp
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@ -90,11 +122,16 @@ class BTBReq extends Bundle with BTBParameters {
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}
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// fully-associative branch target buffer
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class BTB extends Module with BTBParameters {
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// Higher-performance processors may cause BTB updates to occur out-of-order,
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// which requires an extra CAM port for updates (to ensure no duplicates get
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// placed in BTB).
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class BTB(updates_out_of_order: Boolean = false) extends Module with BTBParameters {
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val io = new Bundle {
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val req = Valid(new BTBReq).flip
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val resp = Valid(new BTBResp)
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val update = Valid(new BTBUpdate).flip
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val btb_update = Valid(new BTBUpdate).flip
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val bht_update = Valid(new BHTUpdate).flip
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val ras_update = Valid(new RASUpdate).flip
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val invalidate = Bool(INPUT)
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}
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@ -110,6 +147,7 @@ class BTB extends Module with BTBParameters {
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val useRAS = Reg(UInt(width = entries))
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val isJump = Reg(UInt(width = entries))
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val brIdx = Mem(UInt(width=log2Up(params(FetchWidth))), entries)
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private def page(addr: UInt) = addr >> matchBits
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private def pageMatch(addr: UInt) = {
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@ -123,58 +161,62 @@ class BTB extends Module with BTBParameters {
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idxValid & idxMatch & idxPageMatch
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}
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val r_update = Pipe(io.update)
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val r_btb_update = Pipe(io.btb_update)
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val update_target = io.req.bits.addr
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val pageHit = pageMatch(io.req.bits.addr)
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val hits = tagMatch(io.req.bits.addr, pageHit)
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val updatePageHit = pageMatch(r_update.bits.pc)
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val updateHits = tagMatch(r_update.bits.pc, updatePageHit)
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val updatePageHit = pageMatch(r_btb_update.bits.pc)
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val updateHits = tagMatch(r_btb_update.bits.pc, updatePageHit)
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private var lfsr = LFSR16(r_update.valid)
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private var lfsr = LFSR16(r_btb_update.valid)
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def rand(width: Int) = {
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lfsr = lfsr(lfsr.getWidth-1,1)
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Random.oneHot(width, lfsr)
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}
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val updateHit = r_update.bits.prediction.valid
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val updateValid = r_update.bits.mispredict || updateHit && Bool(nBHT > 0)
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val updateTarget = updateValid && r_update.bits.mispredict && r_update.bits.taken
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val updateHit = r_btb_update.bits.prediction.valid
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val useUpdatePageHit = updatePageHit.orR
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val doIdxPageRepl = updateTarget && !useUpdatePageHit
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val doIdxPageRepl = !useUpdatePageHit
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val idxPageRepl = UInt()
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val idxPageUpdateOH = Mux(useUpdatePageHit, updatePageHit, idxPageRepl)
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val idxPageUpdate = OHToUInt(idxPageUpdateOH)
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val idxPageReplEn = Mux(doIdxPageRepl, idxPageRepl, UInt(0))
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val samePage = page(r_update.bits.pc) === page(update_target)
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val samePage = page(r_btb_update.bits.pc) === page(update_target)
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val usePageHit = (pageHit & ~idxPageReplEn).orR
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val doTgtPageRepl = updateTarget && !samePage && !usePageHit
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val doTgtPageRepl = !samePage && !usePageHit
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val tgtPageRepl = Mux(samePage, idxPageUpdateOH, idxPageUpdateOH(nPages-2,0) << 1 | idxPageUpdateOH(nPages-1))
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val tgtPageUpdate = OHToUInt(Mux(usePageHit, pageHit, tgtPageRepl))
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val tgtPageReplEn = Mux(doTgtPageRepl, tgtPageRepl, UInt(0))
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val doPageRepl = doIdxPageRepl || doTgtPageRepl
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val pageReplEn = idxPageReplEn | tgtPageReplEn
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idxPageRepl := UIntToOH(Counter(r_update.valid && doPageRepl, nPages)._1)
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idxPageRepl := UIntToOH(Counter(r_btb_update.valid && doPageRepl, nPages)._1)
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when (r_update.valid && !(updateValid && !updateTarget)) {
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val nextRepl = Counter(!updateHit && updateValid, entries)._1
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val waddr = Mux(updateHit, r_update.bits.prediction.bits.entry, nextRepl)
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when (r_btb_update.valid) {
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assert(io.req.bits.addr === r_btb_update.bits.target, "BTB request != I$ target")
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val nextRepl = Counter(!updateHit, entries)._1
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val waddr =
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if (updates_out_of_order) Mux(updateHits.orR, OHToUInt(updateHits), nextRepl)
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else Mux(updateHit, r_btb_update.bits.prediction.bits.entry, nextRepl)
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// invalidate entries if we stomp on pages they depend upon
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idxValid := idxValid & ~Vec.tabulate(entries)(i => (pageReplEn & (idxPagesOH(i) | tgtPagesOH(i))).orR).toBits
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idxValid(waddr) := updateValid
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when (updateTarget) {
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assert(io.req.bits.addr === r_update.bits.target, "BTB request != I$ target")
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idxs(waddr) := r_update.bits.pc
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tgts(waddr) := update_target
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idxPages(waddr) := idxPageUpdate
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tgtPages(waddr) := tgtPageUpdate
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useRAS(waddr) := r_update.bits.isReturn
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isJump(waddr) := r_update.bits.isJump
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idxValid(waddr) := Bool(true)
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idxs(waddr) := r_btb_update.bits.pc
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tgts(waddr) := update_target
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idxPages(waddr) := idxPageUpdate
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tgtPages(waddr) := tgtPageUpdate
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useRAS(waddr) := r_btb_update.bits.isReturn
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isJump(waddr) := r_btb_update.bits.isJump
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if (params(FetchWidth) == 1) {
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brIdx(waddr) := UInt(0)
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} else {
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brIdx(waddr) := r_btb_update.bits.br_pc >> log2Up(params(CoreInstBits)/8)
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}
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require(nPages % 2 == 0)
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@ -185,9 +227,9 @@ class BTB extends Module with BTBParameters {
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when (en && pageReplEn(i)) { pages(i) := data }
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writeBank(0, 2, Mux(idxWritesEven, doIdxPageRepl, doTgtPageRepl),
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Mux(idxWritesEven, page(r_update.bits.pc), page(update_target)))
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Mux(idxWritesEven, page(r_btb_update.bits.pc), page(update_target)))
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writeBank(1, 2, Mux(idxWritesEven, doTgtPageRepl, doIdxPageRepl),
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Mux(idxWritesEven, page(update_target), page(r_update.bits.pc)))
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Mux(idxWritesEven, page(update_target), page(r_btb_update.bits.pc)))
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when (doPageRepl) { pageValid := pageValid | pageReplEn }
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}
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@ -201,14 +243,21 @@ class BTB extends Module with BTBParameters {
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io.resp.bits.taken := io.resp.valid
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io.resp.bits.target := Cat(Mux1H(Mux1H(hits, tgtPagesOH), pages), Mux1H(hits, tgts))
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io.resp.bits.entry := OHToUInt(hits)
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io.resp.bits.bridx := brIdx(io.resp.bits.entry)
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if (params(FetchWidth) == 1) {
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io.resp.bits.mask := UInt(1)
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} else {
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// note: btb_resp is clock gated, so the mask is only relevant for the io.resp.valid case
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io.resp.bits.mask := Mux(io.resp.bits.taken, Cat((UInt(1) << brIdx(io.resp.bits.entry))-1, UInt(1)),
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SInt(-1))
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}
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if (nBHT > 0) {
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val bht = new BHT(nBHT)
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val res = bht.get(io.req.bits.addr, io.req.valid && hits.orR && !Mux1H(hits, isJump))
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val update_btb_hit = io.update.bits.prediction.valid
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when (io.update.valid && update_btb_hit && !io.update.bits.isJump) {
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bht.update(io.update.bits.pc, io.update.bits.prediction.bits.bht,
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io.update.bits.taken, io.update.bits.mispredict)
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val update_btb_hit = io.bht_update.bits.prediction.valid
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when (io.bht_update.valid && update_btb_hit) {
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bht.update(io.bht_update.bits.pc, io.bht_update.bits.prediction.bits.bht, io.bht_update.bits.taken, io.bht_update.bits.mispredict)
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}
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when (!res.value(0) && !Mux1H(hits, isJump)) { io.resp.bits.taken := false }
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io.resp.bits.bht := res
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@ -220,13 +269,13 @@ class BTB extends Module with BTBParameters {
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when (!ras.isEmpty && doPeek) {
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io.resp.bits.target := ras.peek
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}
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when (io.update.valid) {
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when (io.update.bits.isCall) {
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ras.push(io.update.bits.returnAddr)
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when (io.ras_update.valid) {
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when (io.ras_update.bits.isCall) {
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ras.push(io.ras_update.bits.returnAddr)
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when (doPeek) {
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io.resp.bits.target := io.update.bits.returnAddr
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io.resp.bits.target := io.ras_update.bits.returnAddr
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}
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}.elsewhen (io.update.bits.isReturn && io.update.bits.prediction.valid) {
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}.elsewhen (io.ras_update.bits.isReturn && io.ras_update.bits.prediction.valid) {
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ras.pop
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}
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}
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@ -9,6 +9,7 @@ import uncore._
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case object BuildFPU extends Field[Option[() => FPU]]
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case object XprLen extends Field[Int]
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case object NMultXpr extends Field[Int]
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case object FetchWidth extends Field[Int]
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case object RetireWidth extends Field[Int]
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case object UseVM extends Field[Boolean]
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case object FastLoadWord extends Field[Boolean]
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@ -20,6 +21,7 @@ case object CoreDCacheReqTagBits extends Field[Int]
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abstract trait CoreParameters extends UsesParameters {
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val xprLen = params(XprLen)
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val coreFetchWidth = params(FetchWidth)
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val coreInstBits = params(CoreInstBits)
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val coreInstBytes = coreInstBits/8
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val coreDataBits = xprLen
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@ -32,6 +34,7 @@ abstract trait CoreParameters extends UsesParameters {
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abstract trait RocketCoreParameters extends CoreParameters
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{
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require(params(FetchWidth) == 1) // for now...
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require(params(RetireWidth) == 1) // for now...
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}
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@ -60,7 +60,7 @@ abstract trait DecodeConstants
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// | | | | | | | | | | | | | | | | | | | | | | csr | | | | amo
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// | | | | | | | | | | | | | | | | | | | | | | | | | | | |
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List(N, X,X,X,X,X,X,X,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, X,X,X,X,X,X,CSR.X,X,X,X,X,X)
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val table: Array[(UInt, List[UInt])]
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}
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@ -505,7 +505,7 @@ class Control extends Module
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when (mem_xcpt) { wb_reg_cause := mem_cause }
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val wb_set_sboard = wb_ctrl.div || wb_dcache_miss || wb_ctrl.rocc
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val replay_wb_common =
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val replay_wb_common =
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io.dmem.resp.bits.nack || wb_reg_replay || io.dpath.csr_replay
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val wb_rocc_val = wb_reg_valid && wb_ctrl.rocc && !replay_wb_common
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val replay_wb = replay_wb_common || wb_reg_valid && wb_ctrl.rocc && !io.rocc.cmd.ready
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@ -558,14 +558,24 @@ class Control extends Module
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Mux(wb_reg_valid && wb_ctrl.sret, PC_PCR, // sret instruction
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PC_MEM)))
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io.imem.btb_update.valid := mem_reg_valid && (mem_ctrl.branch || io.imem.btb_update.bits.isJump) && !take_pc_wb
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io.imem.btb_update.valid := mem_reg_valid && io.dpath.mem_misprediction && ((mem_ctrl.branch && io.dpath.mem_br_taken) || mem_ctrl.jalr || mem_ctrl.jal) && !take_pc_wb
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io.imem.btb_update.bits.prediction.valid := mem_reg_btb_hit
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io.imem.btb_update.bits.prediction.bits := mem_reg_btb_resp
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io.imem.btb_update.bits.taken := mem_ctrl.branch && io.dpath.mem_br_taken || io.imem.btb_update.bits.isJump
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io.imem.btb_update.bits.mispredict := mem_misprediction
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io.imem.btb_update.bits.isJump := mem_ctrl.jal || mem_ctrl.jalr
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io.imem.btb_update.bits.isCall := mem_ctrl.wxd && io.dpath.mem_waddr(0)
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io.imem.btb_update.bits.isReturn := mem_ctrl.jalr && io.dpath.mem_rs1_ra
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io.imem.bht_update.valid := mem_reg_valid && mem_ctrl.branch && !take_pc_wb
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io.imem.bht_update.bits.taken := io.dpath.mem_br_taken
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io.imem.bht_update.bits.mispredict := io.dpath.mem_misprediction
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io.imem.bht_update.bits.prediction.valid := mem_reg_btb_hit
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io.imem.bht_update.bits.prediction.bits := mem_reg_btb_resp
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io.imem.ras_update.valid := io.imem.btb_update.bits.isJump && !take_pc_wb
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io.imem.ras_update.bits.isCall := mem_ctrl.wxd && io.dpath.mem_waddr(0)
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io.imem.ras_update.bits.isReturn := mem_ctrl.jalr && io.dpath.mem_rs1_ra
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io.imem.ras_update.bits.prediction.valid := mem_reg_btb_hit
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io.imem.ras_update.bits.prediction.bits := mem_reg_btb_resp
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io.imem.req.valid := take_pc
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val bypassDst = Array(id_raddr1, id_raddr2)
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@ -595,7 +605,7 @@ class Control extends Module
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io.fpu.dec.ren3 && id_raddr3 === io.dpath.ex_waddr ||
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io.fpu.dec.wen && id_waddr === io.dpath.ex_waddr)
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val id_ex_hazard = ex_reg_valid && (data_hazard_ex && ex_cannot_bypass || fp_data_hazard_ex)
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// stall for RAW/WAW hazards on PCRs, LB/LH, and mul/div in memory stage.
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val mem_mem_cmd_bh =
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if (params(FastLoadWord)) Bool(!params(FastLoadByte)) && mem_reg_slow_bypass
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|
|
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@ -42,9 +42,9 @@ class Datapath extends Module
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val wb_reg_rs2 = Reg(Bits())
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// instruction decode stage
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val id_inst = io.imem.resp.bits.data
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val id_inst = io.imem.resp.bits.data(0).toBits; require(params(FetchWidth) == 1)
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val id_pc = io.imem.resp.bits.pc
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class RegFile {
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private val rf = Mem(UInt(width = 64), 31)
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private val reads = collection.mutable.ArrayBuffer[(UInt,UInt)]()
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@ -276,7 +276,9 @@ class Datapath extends Module
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wb_reg_pc)).toUInt // PC_WB
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io.imem.btb_update.bits.pc := mem_reg_pc
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io.imem.btb_update.bits.target := io.imem.req.bits.pc
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io.imem.btb_update.bits.returnAddr := mem_int_wdata
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io.imem.btb_update.bits.br_pc := mem_reg_pc
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io.imem.bht_update.bits.pc := mem_reg_pc
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io.imem.ras_update.bits.returnAddr := mem_int_wdata
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// for hazard/bypass opportunity detection
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io.ctrl.ex_waddr := ex_reg_inst(11,7)
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|
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@ -1,5 +1,3 @@
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// See LICENSE for license details.
|
||||
|
||||
package rocket
|
||||
|
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import Chisel._
|
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|
|
@ -27,7 +25,8 @@ class FrontendReq extends CoreBundle {
|
|||
|
||||
class FrontendResp extends CoreBundle {
|
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val pc = UInt(width = params(VAddrBits)+1) // ID stage PC
|
||||
val data = Bits(width = coreInstBits)
|
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val data = Vec.fill(coreFetchWidth) (Bits(width = coreInstBits))
|
||||
val mask = Bits(width = coreFetchWidth)
|
||||
val xcpt_ma = Bool()
|
||||
val xcpt_if = Bool()
|
||||
}
|
||||
|
|
@ -37,18 +36,20 @@ class CPUFrontendIO extends CoreBundle {
|
|||
val resp = Decoupled(new FrontendResp).flip
|
||||
val btb_resp = Valid(new BTBResp).flip
|
||||
val btb_update = Valid(new BTBUpdate)
|
||||
val bht_update = Valid(new BHTUpdate)
|
||||
val ras_update = Valid(new RASUpdate)
|
||||
val ptw = new TLBPTWIO().flip
|
||||
val invalidate = Bool(OUTPUT)
|
||||
}
|
||||
|
||||
class Frontend extends FrontendModule
|
||||
class Frontend(btb_updates_out_of_order: Boolean = false) extends FrontendModule
|
||||
{
|
||||
val io = new Bundle {
|
||||
val cpu = new CPUFrontendIO().flip
|
||||
val mem = new UncachedTileLinkIO
|
||||
}
|
||||
|
||||
val btb = Module(new BTB)
|
||||
val btb = Module(new BTB(btb_updates_out_of_order))
|
||||
val icache = Module(new ICache)
|
||||
val tlb = Module(new TLB(params(NITLBEntries)))
|
||||
|
||||
|
|
@ -62,13 +63,14 @@ class Frontend extends FrontendModule
|
|||
val s2_xcpt_if = Reg(init=Bool(false))
|
||||
|
||||
val msb = vaddrBits-1
|
||||
val lsb = log2Up(coreFetchWidth*coreInstBytes)
|
||||
val btbTarget = Cat(btb.io.resp.bits.target(msb), btb.io.resp.bits.target)
|
||||
val pcp4_0 = s1_pc + UInt(coreInstBytes)
|
||||
val pcp4 = Cat(s1_pc(msb) & pcp4_0(msb), pcp4_0(msb,0))
|
||||
val ntpc_0 = s1_pc + UInt(coreInstBytes*coreFetchWidth)
|
||||
val ntpc = Cat(s1_pc(msb) & ntpc_0(msb), ntpc_0(msb,lsb), Bits(0,lsb)) // unsure
|
||||
val icmiss = s2_valid && !icache.io.resp.valid
|
||||
val predicted_npc = Mux(btb.io.resp.bits.taken, btbTarget, pcp4)
|
||||
val predicted_npc = Mux(btb.io.resp.bits.taken, btbTarget, ntpc)
|
||||
val npc = Mux(icmiss, s2_pc, predicted_npc).toUInt
|
||||
val s0_same_block = !icmiss && !io.cpu.req.valid && !btb.io.resp.bits.taken && ((pcp4 & rowBytes) === (s1_pc & rowBytes))
|
||||
val s0_same_block = !icmiss && !io.cpu.req.valid && !btb.io.resp.bits.taken && ((ntpc & rowBytes) === (s1_pc & rowBytes))
|
||||
|
||||
val stall = io.cpu.resp.valid && !io.cpu.resp.ready
|
||||
when (!stall) {
|
||||
|
|
@ -90,7 +92,9 @@ class Frontend extends FrontendModule
|
|||
|
||||
btb.io.req.valid := !stall && !icmiss
|
||||
btb.io.req.bits.addr := s1_pc & SInt(-coreInstBytes)
|
||||
btb.io.update := io.cpu.btb_update
|
||||
btb.io.btb_update := io.cpu.btb_update
|
||||
btb.io.bht_update := io.cpu.bht_update
|
||||
btb.io.ras_update := io.cpu.ras_update
|
||||
btb.io.invalidate := io.cpu.invalidate || io.cpu.ptw.invalidate
|
||||
|
||||
tlb.io.ptw <> io.cpu.ptw
|
||||
|
|
@ -110,7 +114,17 @@ class Frontend extends FrontendModule
|
|||
|
||||
io.cpu.resp.valid := s2_valid && (s2_xcpt_if || icache.io.resp.valid)
|
||||
io.cpu.resp.bits.pc := s2_pc & SInt(-coreInstBytes) // discard PC LSBs
|
||||
io.cpu.resp.bits.data := icache.io.resp.bits.datablock >> (s2_pc(log2Up(rowBytes)-1,log2Up(coreInstBytes)) << log2Up(coreInstBits))
|
||||
|
||||
|
||||
val fetch_data = icache.io.resp.bits.datablock >> (s2_pc(log2Up(rowBytes)-1,log2Up(coreFetchWidth*coreInstBytes)) << log2Up(coreFetchWidth*coreInstBits))
|
||||
for (i <- 0 until coreFetchWidth) {
|
||||
io.cpu.resp.bits.data(i) := fetch_data(i*coreInstBits+coreInstBits-1, i*coreInstBits)
|
||||
}
|
||||
|
||||
val all_ones = UInt((1 << (coreFetchWidth+1))-1)
|
||||
val msk_pc = if (coreFetchWidth == 1) all_ones else all_ones << s2_pc(log2Up(coreFetchWidth) -1+2,2)
|
||||
io.cpu.resp.bits.mask := Mux(s2_btb_resp_valid, msk_pc & s2_btb_resp_bits.mask, msk_pc)
|
||||
|
||||
io.cpu.resp.bits.xcpt_ma := s2_pc(log2Up(coreInstBytes)-1,0) != UInt(0)
|
||||
io.cpu.resp.bits.xcpt_if := s2_xcpt_if
|
||||
|
||||
|
|
|
|||
Loading…
Reference in New Issue
Block a user