riscv/rocket-chip
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Separate exception return control from exception control

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This commit is contained in:
Andrew Waterman 2015-03-17 00:14:32 -07:00
parent e85c54cc4b
commit 2c875555a2
2 changed files with 6 additions and 3 deletions
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4
rocket/src/main/scala/csr.scala
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@ -82,6 +82,7 @@ class CSRFileIO extends CoreBundle {
val csr_replay = Bool(OUTPUT)
val csr_xcpt = Bool(OUTPUT)
val eret = Bool(OUTPUT)
val status = new MStatus().asOutput
val ptbr = UInt(OUTPUT, paddrBits)
@ -206,7 +207,8 @@ class CSRFile extends CoreModule
Mux(insn_redirect_trap, reg_stvec,
Mux(reg_mstatus.prv(1), reg_mepc, reg_sepc))).toUInt
io.ptbr := reg_sptbr
io.csr_xcpt := csr_xcpt || insn_redirect_trap || insn_ret /* sort of a lie */
io.csr_xcpt := csr_xcpt
io.eret := insn_ret || insn_redirect_trap
io.status := reg_mstatus
io.status.fs := reg_mstatus.fs.orR.toSInt // either off or dirty (no clean/initial support yet)
io.status.xs := reg_mstatus.xs.orR.toSInt // either off or dirty (no clean/initial support yet)

5
rocket/src/main/scala/ctrl.scala
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@ -45,6 +45,7 @@ class CtrlDpathIO extends CoreBundle
// inputs from csr file
val csr_replay = Bool(INPUT)
val csr_xcpt = Bool(INPUT)
val eret = Bool(INPUT)
val interrupt = Bool(INPUT)
val interrupt_cause = UInt(INPUT, xLen)
}
@ -541,10 +542,10 @@ class Control extends CoreModule
val wb_xcpt = wb_reg_xcpt || io.dpath.csr_xcpt
// control transfer from ex/wb
take_pc_wb := replay_wb || wb_xcpt
take_pc_wb := replay_wb || wb_xcpt || io.dpath.eret
io.dpath.sel_pc :=
Mux(wb_xcpt, PC_PCR, // exception or [m|s]ret
Mux(wb_xcpt || io.dpath.eret, PC_PCR, // exception or [m|s]ret
Mux(replay_wb, PC_WB, // replay
PC_MEM))