Fixed error with icache/btb resp mask.
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08d2c13330
commit
3be3cd7731
@ -230,9 +230,8 @@ class BTB extends Module with BTBParameters {
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if (params(FetchWidth) == 1) {
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io.resp.bits.mask := UInt(1)
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} else {
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io.resp.bits.mask := Mux(io.resp.valid, Cat((UInt(1) << brIdx(io.resp.bits.entry))-1, UInt(1)),
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((UInt(1) << UInt(params(FetchWidth)))-UInt(1)))
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// val all_ones = UInt((1 << coreFetchWidth)-1)
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// note: btb_resp is clock gated, so the mask is only relevant for the io.resp.valid case
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io.resp.bits.mask := Cat((UInt(1) << brIdx(io.resp.bits.entry))-1, UInt(1))
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}
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if (nBHT > 0) {
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@ -114,9 +114,8 @@ class Frontend extends FrontendModule
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io.cpu.resp.bits.data(i) := fetch_data(i*coreInstBits+coreInstBits-1, i*coreInstBits)
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}
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val all_ones = UInt((1 << coreFetchWidth)-1)
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val all_ones = UInt((1 << (coreFetchWidth+1))-1)
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val msk_pc = if (coreFetchWidth == 1) all_ones else all_ones << s2_pc(log2Up(coreFetchWidth) -1+2,2)
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// TODO what is the best way to handle the clock-gating of s2_btb_resp_bits?
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io.cpu.resp.bits.mask := Mux(s2_btb_resp_valid, msk_pc & s2_btb_resp_bits.mask, msk_pc)
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io.cpu.resp.bits.xcpt_ma := s2_pc(log2Up(coreInstBytes)-1,0) != UInt(0)
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