riscv/rocket-chip
1
0
Fork 0
Code Releases Activity

Commit Graph

  • 1dc8af894e fix serializer/deserializer and add Atos serdes/desser Howard Mao 2016-02-24 21:33:51 -0800
  • 82cacfbc5e add NastiMemoryDemux to unit tests Howard Mao 2016-02-25 13:35:52 -0800
  • 075fdfb847 use Atos serdes/desser in Atos unit test Howard Mao 2016-02-24 21:34:50 -0800
  • ee66da603a move AtosConverterTest into UnitTestSuite Howard Mao 2016-02-23 16:42:19 -0800
  • d19aaf8d89 test AtoS conversions and SERDES Howard Mao 2016-01-21 17:40:30 -0800
  • 7c33d88861 Merge pull request #90 from ucb-bar/elaborate-once Palmer Dabbelt 2016-04-18 21:04:55 -0700
  • 85c86994a0 Bump Chisel3, to elaborate circuits once Palmer Dabbelt 2016-04-18 13:14:59 -0700
  • cbfd7fd13a Remove tracegen scripts, now in groundtest Matthew Naylor 2016-04-06 16:47:43 +0100
  • c5838dd9b3 Fix narrow read/write behavior for AXI converters and fix L2 bugs Howard Mao 2016-04-01 17:53:59 -0700
  • d5153bf42e don't connect unnecessary wires in regression test Howard Mao 2016-04-05 15:05:36 -0700
  • 55df7d97cc add regression test for put immediately before put block Howard Mao 2016-04-04 20:31:14 -0700
  • 485d8d7f9c fix nasti converter tests Howard Mao 2016-04-04 19:49:55 -0700
  • b2e15cd9bc NASTI to SMI converter test should also test TL to NASTI conversion Howard Mao 2016-04-04 12:10:45 -0700
  • 0c562277db test Nasti to SMI converter with SMI datawidth being different Howard Mao 2016-04-01 17:42:36 -0700
  • 152645b1bc use manager_id instead of client_id in GrantFromSrc and FinishToDst Howard Mao 2016-04-07 11:20:16 -0700
  • f88b6932ce don't add pending reads if data is already available Howard Mao 2016-04-06 15:43:21 -0700
  • 2d6f35525e Added Field[Int] to SFMALatency/DFMALatency params Christopher Celio 2016-04-06 14:47:03 -0700
  • a81334f505 Update README links to point to this repo mwachs5 2016-04-06 14:10:04 -0700
  • b2eabf4a9f Add tracegen scripts inc. bugfix from @mwachs5 Matthew Naylor 2016-04-06 15:15:48 +0100
  • 31e145eaf0 fix BroadcastHub allocation and routing Howard Mao 2016-04-05 16:21:18 -0700
  • f68a7dabdf fix AXI -> TL converter Howard Mao 2016-04-04 19:42:25 -0700
  • f956d4edfb NASTI does not right-justify data; fix in converter Howard Mao 2016-04-01 17:42:13 -0700
  • c292a07ace Bugfix for merged voluntary releases in L2Cache. Henry Cook 2016-04-01 19:40:11 -0700
  • 7285f5e6bf Don't drive D$ kill/phys signals for SimpleHellaCacheIF Andrew Waterman 2016-04-01 19:31:54 -0700
  • 51e0870e23 Separate I$ and D$ interface signals that span clock cycles Andrew Waterman 2016-04-01 19:30:39 -0700
  • d66d8f0cd4 fix SMI converter Howard Mao 2016-04-01 17:41:40 -0700
  • c4c6bd1040 Bump rocket. Andrew Waterman 2016-04-01 17:29:31 -0700
  • b43a85e2e8 Make ExampleSmallConfig/DefaultRV32Config smaller Andrew Waterman 2016-04-01 16:41:48 -0700
  • 6878e3265f Default RowBits to TileLink width, not XLen Andrew Waterman 2016-04-01 16:40:30 -0700
  • 46d7dceb1e Disable printf/assert during reset Andrew Waterman 2016-04-01 16:40:13 -0700
  • cd9e07d8e7 Update sbt to 0.13.11 Andrew Waterman 2016-04-01 16:39:47 -0700
  • bd3dba7f66 Fix LR/SC livelock bug Andrew Waterman 2016-04-01 16:38:46 -0700
  • 35d02c5096 LRSC fix. RocketChipNetwork moved to uncore. Henry Cook 2016-04-01 15:38:31 -0700
  • dc662f28a0 Specify width on s1_pc to avoid width inference problem Andrew Waterman 2016-04-01 17:28:42 -0700
  • 72f7f71eb5 No need to allow finishes to be sent in s_refill_resp state Andrew Waterman 2016-04-01 16:19:57 -0700
  • 82bdf3afcb Fix LRSC starvation bug by punching Finish messages out to caching clients via a new TileLinkNetworkPort. Henry Cook 2016-04-01 15:29:52 -0700
  • 78bc18736e LRSC startvation fix: HellaCache generates its own Finish messages again. Henry Cook 2016-04-01 15:34:40 -0700
  • 37b9051762 No need to validate npc if BTB is disabled Andrew Waterman 2016-04-01 15:46:36 -0700
  • 4480d1e817 Don't compile BTB when nEntries=0 Andrew Waterman 2016-04-01 15:14:45 -0700
  • d406dc1231 Remove vestigial BTB enable option Andrew Waterman 2016-04-01 15:14:34 -0700
  • 8957b5e973 Improve simulation speed of BasicCrossbar Andrew Waterman 2016-04-01 13:27:50 -0700
  • 5337c7d22d add more complicated memtests to travis Howard Mao 2016-03-31 18:42:14 -0700
  • 4f06a5ff6b add memtest config for testing memory channel mux Howard Mao 2016-03-31 18:40:35 -0700
  • 5a74a9b1e7 switch memory interconnect from AXI to TileLink Howard Mao 2016-03-31 18:18:30 -0700
  • 3083bbca21 fix TileLink arbiters and add memory interconnect and memory selector Howard Mao 2016-03-31 18:15:51 -0700
  • 54dd82ff76 bugfix for WB data buffer Henry Cook 2016-03-31 15:26:39 -0700
  • 1792d01ce1 fix leaky assert in nbdcache Christopher Celio 2016-03-31 15:55:22 -0700
  • 6d5c98da7d point submodule pointer to proper commit hash Howard Mao 2016-03-31 15:03:33 -0700
  • 7c3b57b8fa switch MMIO network to TileLink Howard Mao 2016-03-30 15:57:13 -0700
  • 6d3bba6cff Tweaks to README.md Matthew Naylor 2016-03-28 19:41:41 +0100
  • 22e7b3ff2f Update README.md mwachs5 2016-03-23 11:57:45 -0700
  • cf363b1fe4 add TileLink interconnect generator Howard Mao 2016-03-31 11:38:54 -0700
  • adb7eacf6e Fix Chisel3 build for XLen=32 Andrew Waterman 2016-03-30 22:48:51 -0700
  • 70664bbca0 Fix Chisel3 build for UseVM=false Andrew Waterman 2016-03-30 22:48:31 -0700
  • ab540d536a bump uncore for split metadata chisel3 fix Howard Mao 2016-03-30 22:11:45 -0700
  • d78066db5c chisel3 fix for split metadata Howard Mao 2016-03-30 22:11:19 -0700
  • c831a0a4e5 use scala firrtl instead of stanza firrtl Howard Mao 2016-03-30 19:35:25 -0700
  • be612e3843 bump rocket and uncore Howard Mao 2016-03-30 19:23:19 -0700
  • 3d990bdbef workaround for Chisel3 name-aliasing issue Howard Mao 2016-03-30 19:15:22 -0700
  • c081a36893 Revert "Bump chisel3 and firrtl, add support for firrtl $ delimiter" Howard Mao 2016-03-30 19:06:32 -0700
  • e77900f540 Revert "switch back to Chisel2 for verilog build for now" Howard Mao 2016-03-30 19:00:38 -0700
  • 8e601f26e1 switch back to the correct chisel3 and firrtl branches Howard Mao 2016-03-30 18:59:33 -0700
  • 8ad8e8a691 Add partial Sv48/Sv57 support Andrew Waterman 2016-03-30 11:01:53 -0700
  • 1e03408323 get rid of mt benchmark suite Howard Mao 2016-03-29 19:56:42 -0700
  • cf716fea58 fix mm_dramsim2 Howard Mao 2016-03-29 13:51:59 -0700
  • 3673365b08 switch back to Chisel2 for verilog build for now Howard Mao 2016-03-28 13:26:04 -0700
  • 265a82427e add DefaultL2Config and DualCoreConfig to travis Howard Mao 2016-03-28 13:25:44 -0700
  • ad93e0226d Changes to prepare for switch to TileLink interconnect Howard Mao 2016-03-28 13:22:00 -0700
  • 5378f79b50 Bump chisel3 and firrtl, add support for firrtl $ delimiter jackkoenig 2016-03-25 17:20:19 -0700
  • 38649bd4c1 some edits to groundtest regression tests Howard Mao 2016-03-25 14:19:52 -0700
  • 9b9c662952 fix w_last wire Howard Mao 2016-03-25 14:19:13 -0700
  • 2b61f28356 don't test DMA controller for now Howard Mao 2016-03-24 19:57:38 -0700
  • e1a03cc9ac fix issue with partial writemasks Howard Mao 2016-03-24 19:52:12 -0700
  • e652821962 Use correct kind of TileLink arbiter Andrew Waterman 2016-03-28 22:53:47 -0700
  • 015992bc9e no longer need MIFMasterTagBits Howard Mao 2016-03-28 12:24:11 -0700
  • 8e7f18084b switch RTC to use TileLink instead of AXI Howard Mao 2016-03-28 12:23:16 -0700
  • 34852e406d fix bug in NastiRouter Howard Mao 2016-03-28 12:22:43 -0700
  • 5ce3527b88 Merge pull request #32 from ucb-bar/pr-btb-masking Andrew Waterman 2016-03-26 18:15:14 -0700
  • f526d380fd separate btb response mask from the frontend mask Christopher Celio 2016-03-26 05:37:26 -0700
  • ed280fb3de Remove empty when statement (???) Andrew Waterman 2016-03-25 15:52:18 -0700
  • 1ae6d09751 Slightly ameliorate D$->I$ critical path via scoreboard Andrew Waterman 2016-03-25 15:29:32 -0700
  • 6c48dc3471 Use more sensible knob values for SmallConfig Andrew Waterman 2016-03-25 14:18:24 -0700
  • cce89f5fbc Bump rocket Andrew Waterman 2016-03-25 14:18:15 -0700
  • a4685a073f Don't instantiate PTW when UseVM=false Andrew Waterman 2016-03-25 14:17:25 -0700
  • 27b3cca046 Discover D$, PTW port counts dynamically Andrew Waterman 2016-03-25 14:16:56 -0700
  • af3bc1cb79 don't use ROM for partial writemask regression Howard Mao 2016-03-25 14:06:06 -0700
  • 5372f181b1 add in missing connections for regression test Howard Mao 2016-03-25 14:05:52 -0700
  • 7f8f138d6a fix addPendingBitWhenPartialWritemask Howard Mao 2016-03-24 19:48:52 -0700
  • 11bd15432a fix bug in RTC Howard Mao 2016-03-24 18:09:37 -0700
  • 00b3908d92 git rid of reorder queue in narrower Howard Mao 2016-03-21 22:59:55 -0700
  • 8d1ba4d1ec Remove hard-coded XLEN values from D$ Andrew Waterman 2016-03-24 14:52:12 -0700
  • d1639416cb Merge pull request #77 from ucb-bar/chisel3 Andrew Waterman 2016-03-24 12:56:36 -0700
  • 39cf945efb Use Chisel 3 to build verilog on Travis Palmer Dabbelt 2016-03-05 19:17:44 -0800
  • cddfdf0929 Add CHISEL_VERSION make argument Palmer Dabbelt 2016-03-05 17:19:53 -0800
  • d697559754 Correct the polarity of the non-backup-memory HTIF Palmer Dabbelt 2016-03-05 21:45:42 -0800
  • 7d5eac189b Bump the uncore for some Chisel3 fixes Palmer Dabbelt 2016-03-23 16:25:11 -0700
  • 4744deec28 Fix the SCR file for Chisel 3 Palmer Dabbelt 2016-03-05 17:20:25 -0800
  • 476db6ef39 Move to a newer Scala version Palmer Dabbelt 2016-03-05 18:42:45 -0800
  • c6e974b110 Merge pull request #30 from ucb-bar/chisel3 Palmer Dabbelt 2016-03-24 11:52:02 -0700
  • 471f4c2695 change WriteMaskedPutBlockRegression for better bug detection Howard Mao 2016-03-23 14:32:18 -0700