LRSC fix. RocketChipNetwork moved to uncore.
This commit is contained in:
Henry Cook
parent
5337c7d22d
commit
35d02c5096
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@ -1,180 +0,0 @@
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// See LICENSE for license details.
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package rocketchip
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import Chisel._
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import uncore._
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import cde.Parameters
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/** RocketChipNetworks combine a TileLink protocol with a particular physical
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* network implementation and chip layout.
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*
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* Specifically, they provide mappings between ClientTileLinkIO/
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* ManagerTileLinkIO channels and LogicalNetwork ports (i.e. generic
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* TileLinkIO with networking headers). Channels coming into the network have
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* appropriate networking headers appended and outgoing channels have their
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* headers stripped.
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*
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* @constructor base class constructor for Rocket NoC
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* @param addrToManagerId a mapping from a physical address to the network
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* id of a coherence manager
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* @param sharerToClientId a mapping from the id of a particular coherent
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* client (as determined by e.g. the directory) and the network id
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* of that client
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* @param clientDepths the depths of the queue that should be used to buffer
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* each channel on the client side of the network
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* @param managerDepths the depths of the queue that should be used to buffer
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* each channel on the manager side of the network
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*/
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abstract class RocketChipNetwork(
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addrToManagerId: UInt => UInt,
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sharerToClientId: UInt => UInt,
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clientDepths: TileLinkDepths,
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managerDepths: TileLinkDepths)
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(implicit p: Parameters) extends TLModule()(p) {
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val nClients = tlNClients
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val nManagers = tlNManagers
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val io = new Bundle {
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val clients = Vec(nClients, new ClientTileLinkIO).flip
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val managers = Vec(nManagers, new ManagerTileLinkIO).flip
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}
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val clients = io.clients.zipWithIndex.map {
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case (c, i) => {
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val port = Module(new ClientTileLinkNetworkPort(i, addrToManagerId))
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val qs = Module(new TileLinkEnqueuer(clientDepths))
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port.io.client <> c
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qs.io.client <> port.io.network
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qs.io.manager
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}
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}
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val managers = io.managers.zipWithIndex.map {
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case (m, i) => {
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val port = Module(new ManagerTileLinkNetworkPort(i, sharerToClientId))
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val qs = Module(new TileLinkEnqueuer(managerDepths))
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port.io.manager <> m
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port.io.network <> qs.io.manager
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qs.io.client
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}
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}
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}
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/** A simple arbiter for each channel that also deals with header-based routing.
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* Assumes a single manager agent. */
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class RocketChipTileLinkArbiter(
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sharerToClientId: UInt => UInt = (u: UInt) => u,
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clientDepths: TileLinkDepths = TileLinkDepths(0,0,0,0,0),
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managerDepths: TileLinkDepths = TileLinkDepths(0,0,0,0,0))
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(implicit p: Parameters)
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extends RocketChipNetwork(u => UInt(0), sharerToClientId, clientDepths, managerDepths)(p)
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with TileLinkArbiterLike
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with PassesId {
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val arbN = nClients
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require(nManagers == 1)
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if(arbN > 1) {
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hookupClientSource(clients.map(_.acquire), managers.head.acquire)
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hookupClientSource(clients.map(_.release), managers.head.release)
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hookupFinish(clients.map(_.finish), managers.head.finish)
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hookupManagerSourceWithHeader(clients.map(_.probe), managers.head.probe)
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hookupManagerSourceWithHeader(clients.map(_.grant), managers.head.grant)
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} else {
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managers.head <> clients.head
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}
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}
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/** Provides a separate physical crossbar for each channel. Assumes multiple manager
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* agents. Managers are assigned to higher physical network port ids than
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* clients, and translations between logical network id and physical crossbar
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* port id are done automatically.
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*/
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class RocketChipTileLinkCrossbar(
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addrToManagerId: UInt => UInt = u => UInt(0),
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sharerToClientId: UInt => UInt = u => u,
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clientDepths: TileLinkDepths = TileLinkDepths(0,0,0,0,0),
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managerDepths: TileLinkDepths = TileLinkDepths(0,0,0,0,0))
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(implicit p: Parameters)
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extends RocketChipNetwork(addrToManagerId, sharerToClientId, clientDepths, managerDepths)(p) {
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val n = p(LNEndpoints)
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val count = tlDataBeats
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// Actually instantiate the particular networks required for TileLink
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val acqNet = Module(new BasicCrossbar(n, new Acquire, count, Some((a: PhysicalNetworkIO[Acquire]) => a.payload.hasMultibeatData())))
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val relNet = Module(new BasicCrossbar(n, new Release, count, Some((r: PhysicalNetworkIO[Release]) => r.payload.hasMultibeatData())))
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val prbNet = Module(new BasicCrossbar(n, new Probe))
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val gntNet = Module(new BasicCrossbar(n, new Grant, count, Some((g: PhysicalNetworkIO[Grant]) => g.payload.hasMultibeatData())))
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val ackNet = Module(new BasicCrossbar(n, new Finish))
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// Aliases for the various network IO bundle types
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type PNIO[T <: Data] = DecoupledIO[PhysicalNetworkIO[T]]
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type LNIO[T <: Data] = DecoupledIO[LogicalNetworkIO[T]]
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type FromCrossbar[T <: Data] = PNIO[T] => LNIO[T]
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type ToCrossbar[T <: Data] = LNIO[T] => PNIO[T]
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// Shims for converting between logical network IOs and physical network IOs
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def crossbarToManagerShim[T <: Data](in: PNIO[T]): LNIO[T] = {
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val out = DefaultFromPhysicalShim(in)
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out.bits.header.src := in.bits.header.src - UInt(nManagers)
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out
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}
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def crossbarToClientShim[T <: Data](in: PNIO[T]): LNIO[T] = {
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val out = DefaultFromPhysicalShim(in)
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out.bits.header.dst := in.bits.header.dst - UInt(nManagers)
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out
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}
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def managerToCrossbarShim[T <: Data](in: LNIO[T]): PNIO[T] = {
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val out = DefaultToPhysicalShim(n, in)
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out.bits.header.dst := in.bits.header.dst + UInt(nManagers)
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out
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}
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def clientToCrossbarShim[T <: Data](in: LNIO[T]): PNIO[T] = {
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val out = DefaultToPhysicalShim(n, in)
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out.bits.header.src := in.bits.header.src + UInt(nManagers)
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out
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}
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// Make an individual connection between virtual and physical ports using
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// a particular shim. Also pin the unused Decoupled control signal low.
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def doDecoupledInputHookup[T <: Data](phys_in: PNIO[T], phys_out: PNIO[T], log_io: LNIO[T], shim: ToCrossbar[T]) = {
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val s = shim(log_io)
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phys_in.valid := s.valid
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phys_in.bits := s.bits
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s.ready := phys_in.ready
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phys_out.ready := Bool(false)
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}
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def doDecoupledOutputHookup[T <: Data](phys_in: PNIO[T], phys_out: PNIO[T], log_io: LNIO[T], shim: FromCrossbar[T]) = {
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val s = shim(phys_out)
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log_io.valid := s.valid
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log_io.bits := s.bits
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s.ready := log_io.ready
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phys_in.valid := Bool(false)
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}
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//Hookup all instances of a particular subbundle of TileLink
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def doDecoupledHookups[T <: Data](physIO: BasicCrossbarIO[T], getLogIO: TileLinkIO => LNIO[T]) = {
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physIO.in.head.bits.payload match {
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case c: ClientToManagerChannel => {
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managers.zipWithIndex.map { case (i, id) =>
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doDecoupledOutputHookup(physIO.in(id), physIO.out(id), getLogIO(i), crossbarToManagerShim[T])
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}
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clients.zipWithIndex.map { case (i, id) =>
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doDecoupledInputHookup(physIO.in(id+nManagers), physIO.out(id+nManagers), getLogIO(i), clientToCrossbarShim[T])
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}
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}
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case m: ManagerToClientChannel => {
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managers.zipWithIndex.map { case (i, id) =>
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doDecoupledInputHookup(physIO.in(id), physIO.out(id), getLogIO(i), managerToCrossbarShim[T])
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}
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clients.zipWithIndex.map { case (i, id) =>
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doDecoupledOutputHookup(physIO.in(id+nManagers), physIO.out(id+nManagers), getLogIO(i), crossbarToClientShim[T])
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}
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}
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}
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}
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doDecoupledHookups(acqNet.io, (tl: TileLinkIO) => tl.acquire)
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doDecoupledHookups(relNet.io, (tl: TileLinkIO) => tl.release)
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doDecoupledHookups(prbNet.io, (tl: TileLinkIO) => tl.probe)
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doDecoupledHookups(gntNet.io, (tl: TileLinkIO) => tl.grant)
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doDecoupledHookups(ackNet.io, (tl: TileLinkIO) => tl.finish)
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}
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@ -228,9 +228,6 @@ class OuterMemorySystem(implicit val p: Parameters) extends Module with HasTopLe
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// Create a simple L1toL2 NoC between the tiles+htif and the banks of outer memory
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// Cached ports are first in client list, making sharerToClientId just an indentity function
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// addrToBank is sed to hash physical addresses (of cache blocks) to banks (and thereby memory channels)
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val ordered_clients = (io.tiles_cached ++
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(io.tiles_uncached ++ Seq(rtc.io, io.htif_uncached))
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.map(TileLinkIOWrapper(_)))
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def sharerToClientId(sharerId: UInt) = sharerId
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def addrToBank(addr: Bits): UInt = {
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Mux(addr.toUInt < UInt(mmioBase >> log2Up(p(CacheBlockBytes))),
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@ -238,8 +235,7 @@ class OuterMemorySystem(implicit val p: Parameters) extends Module with HasTopLe
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UInt(nBanks))
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}
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val preBuffering = TileLinkDepths(2,2,2,2,2)
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val postBuffering = TileLinkDepths(0,0,1,0,0) //TODO: had EOS24 crit path on inner.release
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val l1tol2net = Module(new RocketChipTileLinkCrossbar(addrToBank, sharerToClientId, preBuffering, postBuffering))
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val l1tol2net = Module(new PortedTileLinkCrossbar(addrToBank, sharerToClientId, preBuffering))
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// Create point(s) of coherence serialization
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val managerEndpoints = List.tabulate(nBanks){id => p(BuildL2CoherenceManager)(id, p)}
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@ -253,7 +249,8 @@ class OuterMemorySystem(implicit val p: Parameters) extends Module with HasTopLe
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// Wire the tiles and htif to the TileLink client ports of the L1toL2 network,
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// and coherence manager(s) to the other side
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l1tol2net.io.clients <> ordered_clients
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l1tol2net.io.clients_cached <> io.tiles_cached
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l1tol2net.io.clients_uncached <> io.tiles_uncached ++ Seq(rtc.io, io.htif_uncached)
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l1tol2net.io.managers <> managerEndpoints.map(_.innerTL) :+ mmioManager.io.inner
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// Create a converter between TileLinkIO and MemIO for each channel
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