fix SMI converter
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015992bc9e
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d66d8f0cd4
@ -113,7 +113,6 @@ class SmiIONastiReadIOConverter(val dataWidth: Int, val addrWidth: Int)
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val id = Reg(UInt(width = nastiRIdBits))
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val byteOff = Reg(UInt(width = byteOffBits))
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val sendInd = Reg(init = UInt(0, wordCountBits))
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val recvInd = Reg(init = UInt(0, wordCountBits))
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val sendDone = Reg(init = Bool(false))
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@ -136,32 +135,30 @@ class SmiIONastiReadIOConverter(val dataWidth: Int, val addrWidth: Int)
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when (io.ar.fire()) {
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when (io.ar.bits.size < UInt(byteOffBits)) {
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nWords := UInt(0)
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byteOff := io.ar.bits.addr(byteOffBits - 1, 0)
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} .otherwise {
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nWords := calcWordCount(io.ar.bits.size)
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byteOff := UInt(0)
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}
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nBeats := io.ar.bits.len
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addr := io.ar.bits.addr(addrOffBits - 1, byteOffBits)
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recvInd := io.ar.bits.addr(wordCountBits + byteOffBits - 1, byteOffBits)
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id := io.ar.bits.id
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state := s_read
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}
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when (io.smi.req.fire()) {
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addr := addr + UInt(1)
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sendInd := sendInd + UInt(1)
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sendDone := (sendInd === nWords)
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sendDone := (nWords === UInt(0))
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}
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when (io.smi.resp.fire()) {
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recvInd := recvInd + UInt(1)
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buffer(recvInd) := io.smi.resp.bits >> Cat(byteOff, UInt(0, 3))
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when (recvInd === nWords) { state := s_resp }
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nWords := nWords - UInt(1)
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buffer(recvInd) := io.smi.resp.bits
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when (nWords === UInt(0)) { state := s_resp }
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}
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when (io.r.fire()) {
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recvInd := UInt(0)
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sendInd := UInt(0)
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sendDone := Bool(false)
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// clear all the registers in the buffer
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buffer.foreach(_ := Bits(0))
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@ -183,19 +180,19 @@ class SmiIONastiWriteIOConverter(val dataWidth: Int, val addrWidth: Int)
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private val maxWordsPerBeat = nastiXDataBits / dataWidth
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private val byteOffBits = log2Floor(dataBytes)
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private val addrOffBits = addrWidth + byteOffBits
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private val nastiByteOffBits = log2Ceil(nastiXDataBits / 8)
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assert(!io.aw.valid || io.aw.bits.size >= UInt(byteOffBits),
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"Nasti size must be >= Smi size")
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val id = Reg(UInt(width = nastiWIdBits))
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val addr = Reg(UInt(width = addrWidth))
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val offset = Reg(UInt(width = nastiByteOffBits))
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def makeStrobe(size: UInt, strb: UInt) = {
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def makeStrobe(offset: UInt, size: UInt, strb: UInt) = {
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val sizemask = (UInt(1) << (UInt(1) << size)) - UInt(1)
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val bytemask = sizemask & strb
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val bytemask = strb & (sizemask << offset)
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Vec.tabulate(maxWordsPerBeat){i => bytemask(dataBytes * i)}.toBits
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//val strbmask = Vec.tabulate(maxWordsPerBeat){i => strb(dataBytes * i)}.toBits
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//sizemask & strbmask
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}
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val size = Reg(UInt(width = nastiXSizeBits))
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@ -222,7 +219,13 @@ class SmiIONastiWriteIOConverter(val dataWidth: Int, val addrWidth: Int)
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else UInt(1)
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when (io.aw.fire()) {
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addr := io.aw.bits.addr(addrOffBits - 1, byteOffBits)
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if (dataWidth == nastiXDataBits) {
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addr := io.aw.bits.addr(addrOffBits - 1, byteOffBits)
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} else {
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addr := Cat(io.aw.bits.addr(addrOffBits - 1, nastiByteOffBits),
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UInt(0, nastiByteOffBits - byteOffBits))
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}
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offset := io.aw.bits.addr(nastiByteOffBits - 1, 0)
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id := io.aw.bits.id
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size := io.aw.bits.size
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last := Bool(false)
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@ -231,7 +234,7 @@ class SmiIONastiWriteIOConverter(val dataWidth: Int, val addrWidth: Int)
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when (io.w.fire()) {
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last := io.w.bits.last
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strb := makeStrobe(size, io.w.bits.strb)
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strb := makeStrobe(offset, size, io.w.bits.strb)
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data := io.w.bits.data
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state := s_send
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}
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@ -259,7 +262,9 @@ class SmiIONastiIOConverter(val dataWidth: Int, val addrWidth: Int)
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val smi = new SmiIO(dataWidth, addrWidth)
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}
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require(isPow2(dataWidth), "Smi data width must be power of 2")
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require(isPow2(dataWidth), "SMI data width must be power of 2")
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require(dataWidth <= nastiXDataBits,
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"SMI data width must be less than or equal to NASTI data width")
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val reader = Module(new SmiIONastiReadIOConverter(dataWidth, addrWidth))
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reader.io.ar <> io.nasti.ar
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