fix mm_dramsim2
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parent
3673365b08
commit
cf716fea58
@ -17,17 +17,19 @@ using namespace DRAMSim;
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void mm_dramsim2_t::read_complete(unsigned id, uint64_t address, uint64_t clock_cycle)
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{
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auto req = rreq[address];
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auto req = rreq[address].front();
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for (int i = 0; i < req.len; i++) {
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auto dat = read(address + i * req.size, req.size);
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rresp.push(mm_rresp_t(req.id, dat, (i == req.len - 1)));
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}
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rreq[address].pop();
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}
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void mm_dramsim2_t::write_complete(unsigned id, uint64_t address, uint64_t clock_cycle)
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{
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auto b_id = wreq[address];
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auto b_id = wreq[address].front();
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bresp.push(b_id);
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wreq[address].pop();
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}
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void power_callback(double a, double b, double c, double d)
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@ -82,7 +84,7 @@ void mm_dramsim2_t::tick(
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bool b_fire = b_valid() && b_ready;
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if (ar_fire) {
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rreq[ar_addr] = mm_req_t(ar_id, 1 << ar_size, ar_len + 1, ar_addr);
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rreq[ar_addr].push(mm_req_t(ar_id, 1 << ar_size, ar_len + 1, ar_addr));
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mem->addTransaction(false, ar_addr);
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}
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@ -102,7 +104,7 @@ void mm_dramsim2_t::tick(
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if (store_count == 0) {
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store_inflight = false;
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mem->addTransaction(true, store_addr);
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wreq[store_addr] = store_id;
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wreq[store_addr].push(store_id);
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assert(w_last);
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}
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}
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@ -86,9 +86,9 @@ class mm_dramsim2_t : public mm_t
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uint64_t store_count;
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std::vector<char> dummy_data;
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std::queue<uint64_t> bresp;
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std::map<uint64_t, uint64_t> wreq;
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std::map<uint64_t, std::queue<uint64_t> > wreq;
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std::map<uint64_t, mm_req_t> rreq;
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std::map<uint64_t, std::queue<mm_req_t> > rreq;
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std::queue<mm_rresp_t> rresp;
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void read_complete(unsigned id, uint64_t address, uint64_t clock_cycle);
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