riscv/rocket-chip
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Use Chisel 3 to build verilog on Travis

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Chisel 3 can't build the C++ emulator, so we currently can't have direct
support for testing RocketChip.  We can at least test to see if the
Verilog builds when run through Chisel 3, which this patch does.
This commit is contained in:
Palmer Dabbelt 2016-03-05 19:17:44 -08:00 committed by Palmer Dabbelt
parent cddfdf0929
commit 39cf945efb
1 changed files with 1 additions and 1 deletions
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.travis.yml
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@ -63,7 +63,7 @@ before_install:
- export CXX=g++-4.8 CC=gcc-4.8
script:
- make vsim-verilog -C regression CONFIG=$CONFIG TORTURE_CONFIG=default
- make vsim-verilog -C regression CONFIG=$CONFIG TORTURE_CONFIG=default CHISEL_VERSION=3
- make fsim-verilog -C regression CONFIG=$CONFIG TORTURE_CONFIG=default
- make emulator-ndebug -C regression CONFIG=$CONFIG TORTURE_CONFIG=default
- make emulator-asm-tests -C regression CONFIG=$CONFIG TORTURE_CONFIG=default