riscv/rocket-chip
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switch MMIO network to TileLink

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Howard Mao 2016-03-30 15:57:13 -07:00 committed by Henry Cook
parent ab540d536a
commit 7c3b57b8fa
3 changed files with 39 additions and 15 deletions
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17
src/main/scala/Configs.scala
View File

@ -208,7 +208,8 @@ class DefaultConfig extends Config (
dataBits = site(CacheBlockBytes)*8)
case TLKey("L2toMC") =>
TileLinkParameters(
coherencePolicy = new MEICoherence(new NullRepresentation(site(NBanksPerMemoryChannel))),
coherencePolicy = new MEICoherence(
new NullRepresentation(site(NBanksPerMemoryChannel))),
nManagers = 1,
nCachingClients = site(NBanksPerMemoryChannel),
nCachelessClients = 0,
@ -217,6 +218,20 @@ class DefaultConfig extends Config (
maxManagerXacts = 1,
dataBits = site(CacheBlockBytes)*8)
case TLKey("Outermost") => site(TLKey("L2toMC")).copy(dataBeats = site(MIFDataBeats))
case TLKey("L2toMMIO") => {
val addrMap = new AddrHashMap(site(GlobalAddrMap), site(MMIOBase))
TileLinkParameters(
coherencePolicy = new MICoherence(
new NullRepresentation(site(NBanksPerMemoryChannel))),
nManagers = addrMap.nEntries,
nCachingClients = 0,
nCachelessClients = 1,
maxClientXacts = 4,
maxClientsPerPort = 1,
maxManagerXacts = 1,
dataBits = site(CacheBlockBytes) * 8)
}
case TLKey("MMIO_Outermost") => site(TLKey("L2toMMIO")).copy(dataBeats = site(MIFDataBeats))
case NTiles => Knob("NTILES")
case NMemoryChannels => Dump("N_MEM_CHANNELS", 1)
case NBanksPerMemoryChannel => Knob("NBANKS_PER_MEM_CHANNEL")

35
src/main/scala/RocketChip.scala
View File

@ -248,10 +248,9 @@ class OuterMemorySystem(implicit val p: Parameters) extends Module with HasTopLe
val mmioManager = Module(new MMIOTileLinkManager()(p.alterPartial({
case TLId => "L1toL2"
case InnerTLId => "L1toL2"
case OuterTLId => "L2toMC"
case OuterTLId => "L2toMMIO"
})))
// Wire the tiles and htif to the TileLink client ports of the L1toL2 network,
// and coherence manager(s) to the other side
l1tol2net.io.clients <> ordered_clients
@ -274,8 +273,6 @@ class OuterMemorySystem(implicit val p: Parameters) extends Module with HasTopLe
println("Generated Configuration String")
println(new String(p(ConfigString)))
val mmio_ic = Module(new NastiRecursiveInterconnect(1, nSlaves, addrMap, mmioBase))
val channelConfigs = p(MemoryChannelMuxConfigs)
require(channelConfigs.sortWith(_ > _)(0) == nMemChannels,
"More memory channels elaborated than can be enabled")
@ -300,34 +297,46 @@ class OuterMemorySystem(implicit val p: Parameters) extends Module with HasTopLe
TopUtils.connectNasti(mem_ic.io.masters(i), conv.io.nasti)
}
val mmio_narrow = Module(new TileLinkIONarrower("L2toMC", "Outermost"))
val mmio_conv = Module(new NastiIOTileLinkIOConverter()(outermostTLParams))
mmio_narrow.io.in <> mmioManager.io.outer
mmio_conv.io.tl <> mmio_narrow.io.out
TopUtils.connectNasti(mmio_ic.io.masters(0), mmio_conv.io.nasti)
val mmioOutermostTLParams = p.alterPartial({case TLId => "MMIO_Outermost"})
val mmio_narrow = Module(new TileLinkIONarrower("L2toMMIO", "MMIO_Outermost"))
val mmio_net = Module(new TileLinkRecursiveInterconnect(
1, addrHashMap.nEntries, addrMap, mmioBase)(mmioOutermostTLParams))
//val mmio_conv = Module(new NastiIOTileLinkIOConverter()(outermostTLParams))
mmio_narrow.io.in <> mmioManager.io.outer
mmio_net.io.in.head <> mmio_narrow.io.out
def connectTilelinkNasti(nasti: NastiIO, tl: ClientUncachedTileLinkIO) = {
val conv = Module(new NastiIOTileLinkIOConverter()(mmioOutermostTLParams))
conv.io.tl <> tl
TopUtils.connectNasti(nasti, conv.io.nasti)
}
for (i <- 0 until nTiles) {
val csrName = s"conf:csr$i"
val csrPort = addrHashMap(csrName).port
val conv = Module(new SmiIONastiIOConverter(xLen, csrAddrBits))
conv.io.nasti <> mmio_ic.io.slaves(csrPort)
connectTilelinkNasti(conv.io.nasti, mmio_net.io.out(csrPort))
io.csr(i) <> conv.io.smi
}
val scrPort = addrHashMap("conf:scr").port
val scr_conv = Module(new SmiIONastiIOConverter(scrDataBits, scrAddrBits))
scr_conv.io.nasti <> mmio_ic.io.slaves(addrHashMap("conf:scr").port)
connectTilelinkNasti(scr_conv.io.nasti, mmio_net.io.out(scrPort))
io.scr <> scr_conv.io.smi
if (p(UseStreamLoopback)) {
val lo_width = p(StreamLoopbackWidth)
val lo_size = p(StreamLoopbackSize)
val lo_conv = Module(new NastiIOStreamIOConverter(lo_width))
lo_conv.io.nasti <> mmio_ic.io.slaves(addrHashMap("devices:loopback").port)
val lo_port = addrHashMap("devices:loopback").port
connectTilelinkNasti(lo_conv.io.nasti, mmio_net.io.out(lo_port))
lo_conv.io.stream.in <> Queue(lo_conv.io.stream.out, lo_size)
}
io.deviceTree <> mmio_ic.io.slaves(addrHashMap("conf:devicetree").port)
val dtPort = addrHashMap("conf:devicetree").port
connectTilelinkNasti(io.deviceTree, mmio_net.io.out(dtPort))
val mem_channels = mem_ic.io.slaves
// Create a SerDes for backup memory port

2
uncore

@ -1 +1 @@
Subproject commit fe8d07643a0ed11279969b2ef0cc0319e7d663b1
Subproject commit 23c1d1edf3481d1d90e8280622e2ceedbd3bcab7