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Changes to prepare for switch to TileLink interconnect 

We are planning on switching to a TileLink interconnect throughout and
convert to AXI only on the very edge. Therefore, we need to get rid of
all the existing AXI masters other than the TileLink to AXI converter.

* Get rid of DMA engine for now
* Connect RTC to TileLink interconnect instead of AXI interconnect
This commit is contained in:
Howard Mao 2016-03-28 13:22:00 -07:00
parent 5378f79b50
commit ad93e0226d
5 changed files with 30 additions and 48 deletions
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2
junctions

@ -1 +1 @@
Subproject commit b0fa161f600cfa31f59bcae77b2fe7c97882b319
Subproject commit a43e687ad03708d367f86cb7bc13f66431b1d442

33
src/main/scala/Configs.scala
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@ -80,14 +80,9 @@ class DefaultConfig extends Config (
case ASIdBits => 7
case MIFTagBits => Dump("MIF_TAG_BITS",
// Bits needed at the L2 agent
site(MIFMasterTagBits) +
log2Up(site(NAcquireTransactors)+2) +
// Bits added by NASTI interconnect
max(log2Up(site(MaxBanksPerMemoryChannel)),
(if (site(UseDma)) 3 else 2)))
case MIFMasterTagBits => log2Up(max_int(
site(NTiles),
site(NAcquireTransactors)+2,
site(NDmaTransactors)))
log2Up(site(MaxBanksPerMemoryChannel)))
case MIFDataBits => Dump("MIF_DATA_BITS", 64)
case MIFAddrBits => Dump("MIF_ADDR_BITS",
site(PAddrBits) - site(CacheBlockOffsetBits))
@ -158,7 +153,6 @@ class DefaultConfig extends Config (
case RoccNMemChannels => site(BuildRoCC).map(_.nMemChannels).foldLeft(0)(_ + _)
case RoccNPTWPorts => site(BuildRoCC).map(_.nPTWPorts).foldLeft(0)(_ + _)
case RoccNCSRs => site(BuildRoCC).map(_.csrs.size).foldLeft(0)(_ + _)
case UseDma => false
case UseStreamLoopback => false
case NDmaTransactors => 3
case NDmaXacts => site(NDmaTransactors) * site(NTiles)
@ -192,20 +186,24 @@ class DefaultConfig extends Config (
case LNEndpoints => site(TLKey(site(TLId))).nManagers + site(TLKey(site(TLId))).nClients
case LNHeaderBits => log2Ceil(site(TLKey(site(TLId))).nManagers) +
log2Up(site(TLKey(site(TLId))).nClients)
case ExtraL1Clients => 2 // RTC and HTIF
case TLKey("L1toL2") =>
TileLinkParameters(
coherencePolicy = new MESICoherence(site(L2DirectoryRepresentation)),
nManagers = site(NBanksPerMemoryChannel)*site(NMemoryChannels) + 1,
nCachingClients = site(NTiles),
nCachelessClients = (if (site(UseDma)) 2 else 1) +
nCachelessClients = site(ExtraL1Clients) +
site(NTiles) *
(1 + (if(site(BuildRoCC).isEmpty) 0
else site(RoccNMemChannels))),
maxClientXacts = max_int(site(NMSHRs) + 1,
if (site(BuildRoCC).isEmpty) 1 else site(RoccMaxTaggedMemXacts),
if (site(UseDma)) 4 else 1),
maxClientsPerPort = max(if (site(BuildRoCC).isEmpty) 1 else 2,
if (site(UseDma)) site(NDmaTransactors) + 1 else 1),
maxClientXacts = max_int(
// L1 cache
site(NMSHRs) + 1,
// RoCC
if (site(BuildRoCC).isEmpty) 1 else site(RoccMaxTaggedMemXacts),
// RTC
site(NTiles)),
maxClientsPerPort = if (site(BuildRoCC).isEmpty) 1 else 2,
maxManagerXacts = site(NAcquireTransactors) + 2,
dataBits = site(CacheBlockBytes)*8)
case TLKey("L2toMC") =>
@ -244,9 +242,6 @@ class DefaultConfig extends Config (
if (site(UseStreamLoopback)) {
devset.addDevice("loopback", site(StreamLoopbackWidth) / 8, "stream")
}
if (site(UseDma)) {
devset.addDevice("dma", site(CacheBlockBytes), "dma")
}
devset
}
}},
@ -430,7 +425,6 @@ class RoccExampleConfig extends Config(new WithRoccExample ++ new DefaultConfig)
class WithDmaController extends Config(
(pname, site, here) => pname match {
case UseDma => true
case BuildRoCC => Seq(
RoccParameters(
opcodes = OpcodeSet.custom2,
@ -450,7 +444,6 @@ class WithStreamLoopback extends Config(
})
class DmaControllerConfig extends Config(new WithDmaController ++ new WithStreamLoopback ++ new DefaultL2Config)
class DualCoreDmaControllerConfig extends Config(new With2Cores ++ new DmaControllerConfig)
class DmaControllerFPGAConfig extends Config(new WithDmaController ++ new WithStreamLoopback ++ new DefaultFPGAConfig)
class SmallL2Config extends Config(
@ -478,3 +471,5 @@ class OneOrEightChannelBackupMemVLSIConfig extends Config(new WithOneOrMaxChanne
class WithSplitL2Metadata extends Config(knobValues = { case "L2_SPLIT_METADATA" => true })
class SplitL2MetadataTestConfig extends Config(new WithSplitL2Metadata ++ new DefaultL2Config)
class DualCoreConfig extends Config(new With2Cores ++ new DefaultConfig)

28
src/main/scala/RocketChip.scala
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@ -33,10 +33,10 @@ case object UseHtifClockDiv extends Field[Boolean]
case object BuildL2CoherenceManager extends Field[(Int, Parameters) => CoherenceAgent]
/** Function for building some kind of tile connected to a reset signal */
case object BuildTiles extends Field[Seq[(Bool, Parameters) => Tile]]
/** Enable DMA engine */
case object UseDma extends Field[Boolean]
/** A string describing on-chip devices, readable by target software */
case object ConfigString extends cde.Field[Array[Byte]]
case object ConfigString extends Field[Array[Byte]]
/** Number of L1 clients besides the CPU cores */
case object ExtraL1Clients extends Field[Int]
case object UseStreamLoopback extends Field[Boolean]
case object StreamLoopbackSize extends Field[Int]
@ -45,11 +45,10 @@ case object StreamLoopbackWidth extends Field[Int]
/** Utility trait for quick access to some relevant parameters */
trait HasTopLevelParameters {
implicit val p: Parameters
lazy val useDma = p(UseDma)
lazy val nTiles = p(NTiles)
lazy val nCachedTilePorts = p(TLKey("L1toL2")).nCachingClients
lazy val nUncachedTilePorts =
p(TLKey("L1toL2")).nCachelessClients - (if (useDma) 2 else 1)
p(TLKey("L1toL2")).nCachelessClients - p(ExtraL1Clients)
lazy val htifW = p(HtifKey).width
lazy val csrAddrBits = 12
lazy val nMemChannels = p(NMemoryChannels)
@ -222,17 +221,15 @@ class OuterMemorySystem(implicit val p: Parameters) extends Module with HasTopLe
val deviceTree = new NastiIO
}
val dmaOpt = if (p(UseDma))
Some(Module(new DmaEngine(
DmaCtrlRegNumbers.CSR_BASE + DmaCtrlRegNumbers.OUTSTANDING)))
else None
val mmioBase = p(MMIOBase)
val rtc = Module(new RTC(CSRs.mtime))
// Create a simple L1toL2 NoC between the tiles+htif and the banks of outer memory
// Cached ports are first in client list, making sharerToClientId just an indentity function
// addrToBank is sed to hash physical addresses (of cache blocks) to banks (and thereby memory channels)
val ordered_clients = (io.tiles_cached ++
(io.tiles_uncached ++ dmaOpt.map(_.io.mem) :+ io.htif_uncached)
(io.tiles_uncached ++ Seq(rtc.io, io.htif_uncached))
.map(TileLinkIOWrapper(_)))
def sharerToClientId(sharerId: UInt) = sharerId
def addrToBank(addr: Bits): UInt = {
@ -254,6 +251,7 @@ class OuterMemorySystem(implicit val p: Parameters) extends Module with HasTopLe
case OuterTLId => "L2toMC"
})))
// Wire the tiles and htif to the TileLink client ports of the L1toL2 network,
// and coherence manager(s) to the other side
l1tol2net.io.clients <> ordered_clients
@ -266,7 +264,6 @@ class OuterMemorySystem(implicit val p: Parameters) extends Module with HasTopLe
val addrMap = p(GlobalAddrMap)
val addrHashMap = new AddrHashMap(addrMap, mmioBase)
val nMasters = (if (dmaOpt.isEmpty) 2 else 3)
val nSlaves = addrHashMap.nEntries
// TODO: the code to print this stuff should live somewhere else
@ -277,7 +274,7 @@ class OuterMemorySystem(implicit val p: Parameters) extends Module with HasTopLe
println("Generated Configuration String")
println(new String(p(ConfigString)))
val mmio_ic = Module(new NastiRecursiveInterconnect(nMasters, nSlaves, addrMap, mmioBase))
val mmio_ic = Module(new NastiRecursiveInterconnect(1, nSlaves, addrMap, mmioBase))
val channelConfigs = p(MemoryChannelMuxConfigs)
require(channelConfigs.sortWith(_ > _)(0) == nMemChannels,
@ -309,13 +306,6 @@ class OuterMemorySystem(implicit val p: Parameters) extends Module with HasTopLe
mmio_conv.io.tl <> mmio_narrow.io.out
TopUtils.connectNasti(mmio_ic.io.masters(0), mmio_conv.io.nasti)
val rtc = Module(new RTC(CSRs.mtime))
mmio_ic.io.masters(1) <> rtc.io
dmaOpt.foreach { dma =>
mmio_ic.io.masters(2) <> dma.io.mmio
dma.io.ctrl <> mmio_ic.io.slaves(addrHashMap("devices:dma").port)
}
for (i <- 0 until nTiles) {
val csrName = s"conf:csr$i"

13
src/main/scala/TestConfigs.scala
View File

@ -17,12 +17,11 @@ class WithGroundTest extends Config(
coherencePolicy = new MESICoherence(site(L2DirectoryRepresentation)),
nManagers = site(NBanksPerMemoryChannel)*site(NMemoryChannels) + 1,
nCachingClients = site(NTiles),
nCachelessClients = site(NTiles) + (if (site(UseDma)) 2 else 1),
maxClientXacts = max_int(site(NMSHRs) + 1,
if (site(BuildRoCC).isEmpty) 1 else site(RoccMaxTaggedMemXacts),
if (site(UseDma)) 4 else 1),
maxClientsPerPort = max(if (site(BuildRoCC).isEmpty) 1 else 2,
if (site(UseDma)) site(NDmaTransactors) + 1 else 1),
nCachelessClients = site(NTiles) + site(ExtraL1Clients),
maxClientXacts = max(
site(NMSHRs) + 1,
if (site(BuildRoCC).isEmpty) 1 else site(RoccMaxTaggedMemXacts)),
maxClientsPerPort = if (site(BuildRoCC).isEmpty) 1 else 2,
maxManagerXacts = site(NAcquireTransactors) + 2,
dataBits = site(CacheBlockBytes)*8)
case BuildTiles => {
@ -81,7 +80,6 @@ class WithCacheRegressionTest extends Config(
class WithDmaTest extends Config(
(pname, site, here) => pname match {
case UseDma => true
case BuildGroundTest =>
(id: Int, p: Parameters) => Module(new DmaTest()(p))
case DmaTestSet => DmaTestCases(
@ -97,7 +95,6 @@ class WithDmaTest extends Config(
class WithDmaStreamTest extends Config(
(pname, site, here) => pname match {
case UseDma => true
case BuildGroundTest =>
(id: Int, p: Parameters) => Module(new DmaStreamTest()(p))
case DmaStreamTestSettings => DmaStreamTestConfig(

2
uncore

@ -1 +1 @@
Subproject commit 9978139f4f6276db01b2a46b3438ef0fe73d9d59
Subproject commit b81faf8f8c5800434cfe173d2b859a5203cbaeb5