fix BroadcastHub allocation and routing
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parent
f68a7dabdf
commit
31e145eaf0
@ -73,7 +73,8 @@ class L2BroadcastHub(implicit p: Parameters) extends ManagerCoherenceAgent()(p)
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trackerList.map(_.io.matches.iacq),
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trackerList.map(_.io.alloc.iacq),
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Some(sdqLoc),
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Some(sdq_rdy && !irel_vs_iacq_conflict))
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Some(sdq_rdy && !irel_vs_iacq_conflict),
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Some(sdq_rdy))
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// Queue to store impending Voluntary Release data
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val voluntary = io.irel().isVoluntary()
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@ -77,18 +77,20 @@ trait HasCoherenceAgentWiringHelpers {
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matches: Seq[Bool],
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allocs: Seq[Bool],
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dataOverrides: Option[Seq[UInt]] = None,
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allocOverride: Option[Bool] = None) {
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allocOverride: Option[Bool] = None,
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matchOverride: Option[Bool] = None) {
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val ready_bits = Vec(outs.map(_.ready)).toBits
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val alloc_bits = PriorityEncoderOH(ready_bits)
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val match_bits = Vec(matches).toBits
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val no_matches = !match_bits.orR
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val do_alloc = allocOverride.getOrElse(Bool(true))
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in.ready := Mux(no_matches, ready_bits.orR, (match_bits & ready_bits).orR) && do_alloc
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val alloc_ok = allocOverride.getOrElse(Bool(true))
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val match_ok = matchOverride.getOrElse(Bool(true))
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in.ready := Mux(no_matches, ready_bits.orR, (match_bits & ready_bits).orR) && alloc_ok && match_ok
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outs.zip(allocs).zipWithIndex.foreach { case((out, a), i) =>
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out.valid := in.valid
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out.valid := in.valid && match_ok
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out.bits := in.bits
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dataOverrides foreach { d => out.bits.data := d(i) }
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a := alloc_bits(i) & no_matches & do_alloc
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a := alloc_bits(i) & no_matches & alloc_ok
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}
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}
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}
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