riscv/rocket-chip
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fix BroadcastHub allocation and routing

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This commit is contained in:
Howard Mao
2016-04-05 16:21:18 -07:00
parent f68a7dabdf
commit 31e145eaf0
2 changed files with 9 additions and 6 deletions
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3
uncore/src/main/scala/broadcast.scala
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@@ -73,7 +73,8 @@ class L2BroadcastHub(implicit p: Parameters) extends ManagerCoherenceAgent()(p)
trackerList.map(_.io.matches.iacq),
trackerList.map(_.io.alloc.iacq),
Some(sdqLoc),
Some(sdq_rdy && !irel_vs_iacq_conflict))
Some(sdq_rdy && !irel_vs_iacq_conflict),
Some(sdq_rdy))
// Queue to store impending Voluntary Release data
val voluntary = io.irel().isVoluntary()

12
uncore/src/main/scala/uncore.scala
View File

@@ -77,18 +77,20 @@ trait HasCoherenceAgentWiringHelpers {
matches: Seq[Bool],
allocs: Seq[Bool],
dataOverrides: Option[Seq[UInt]] = None,
allocOverride: Option[Bool] = None) {
allocOverride: Option[Bool] = None,
matchOverride: Option[Bool] = None) {
val ready_bits = Vec(outs.map(_.ready)).toBits
val alloc_bits = PriorityEncoderOH(ready_bits)
val match_bits = Vec(matches).toBits
val no_matches = !match_bits.orR
val do_alloc = allocOverride.getOrElse(Bool(true))
in.ready := Mux(no_matches, ready_bits.orR, (match_bits & ready_bits).orR) && do_alloc
val alloc_ok = allocOverride.getOrElse(Bool(true))
val match_ok = matchOverride.getOrElse(Bool(true))
in.ready := Mux(no_matches, ready_bits.orR, (match_bits & ready_bits).orR) && alloc_ok && match_ok
outs.zip(allocs).zipWithIndex.foreach { case((out, a), i) =>
out.valid := in.valid
out.valid := in.valid && match_ok
out.bits := in.bits
dataOverrides foreach { d => out.bits.data := d(i) }
a := alloc_bits(i) & no_matches & do_alloc
a := alloc_bits(i) & no_matches & alloc_ok
}
}
}