riscv/rocket-chip
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fix issue with partial writemasks

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This commit is contained in:
Howard Mao 2016-03-24 19:52:12 -07:00
parent 6c48dc3471
commit e1a03cc9ac
3 changed files with 6 additions and 2 deletions
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2
groundtest

@ -1 +1 @@
Subproject commit e711f7988fe5be7881406eb310501cc0a7efb098
Subproject commit 109f29e0ae503e6678d0d25213f859339a4f0e33

4
src/main/scala/TestConfigs.scala
View File

@ -35,6 +35,8 @@ class WithGroundTest extends Config(
}
}
case GroundTestMaxXacts => 1
case GroundTestCSRs => Nil
case RoccNCSRs => site(GroundTestCSRs).size
case UseFPU => false
})
@ -101,6 +103,8 @@ class WithDmaStreamTest extends Config(
case DmaStreamTestSettings => DmaStreamTestConfig(
source = 0x10, dest = 0x28, len = 0x18,
size = site(StreamLoopbackWidth) / 8)
case GroundTestCSRs =>
Seq(DmaCtrlRegNumbers.CSR_BASE + DmaCtrlRegNumbers.OUTSTANDING)
})
class WithNastiConverterTest extends Config(

2
uncore

@ -1 +1 @@
Subproject commit 86f6845288d2d8feaa187331acd5a04d8cb1371e
Subproject commit 9978139f4f6276db01b2a46b3438ef0fe73d9d59