Tweaks to README.md
Remove occurrences of ../scripts/ and instead state that it must be in your PATH. Also drop the content introducing the isit script as tracegen+check.sh subsumes this.
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Matthew Naylor
Henry Cook
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@ -42,18 +42,21 @@ The usual Make targets run-asm-tests and run-bmark-tests still work for these co
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## Using TraceGenConfig
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The trace generator in groundtest (tracegen.scala) has the ability to generate random memory-subsystem traces, i.e. random sequences of memory requests, along with their responses. The idea is that these traces can be validated by an external checker, such as [axe](https://github.com/CTSRD-CHERI/axe).
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The trace generator in groundtest
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([tracegen.scala](https://github.com/ucb-bar/groundtest/blob/master/src/main/scala/tracegen.scala)) has the ability to generate random memory-subsystem traces, i.e. random sequences of memory requests, along with their responses. The idea is that these traces can be validated by an external checker, such as [axe](https://github.com/CTSRD-CHERI/axe).
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Putting the generator and the checker together, we can automatically search for invalid traces, i.e. possible bugs in the memory subsystem. This is useful for intensive testing, but also debugging: it is possible to search for simple failing cases.
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### Quick Reference
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The tracegen+check.sh script (included in rocket-chip/scripts) provides an automated way to run a number of randomized tests. The number of tests, initial seed, and other parameters can be set via environment variables or the command line, see the script for more details.
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The [tracegen+check.sh](https://github.com/ucb-bar/rocket-chip/blob/master/scripts/tracegen%2Bcheck.sh) script (included in rocket-chip/scripts) provides an automated way to run a number of randomized tests. The number of tests, initial seed, and other parameters can be set via environment variables or the command line, see the script for more details.
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The examples that follow assume that the rocket-chip/scripts directory is
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in your PATH and that rocket-chip is your current working directory.
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```
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> cd emulator
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> make CONFIG=TraceGenConfig
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> ../scripts/tracegen+check.sh
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> tracegen+check.sh
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Testing against WMO model:
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0: .......... .......... .......... .......... ..........
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@ -66,14 +69,15 @@ Load-external rate: 47%
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### Running Manually
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```
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(in rocket-chip)
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To run a single test with a specified random seed:
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cd emulator
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make CONFIG=TraceGenConfig
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../scripts/tracegen.py ./emulator-Top-TraceGenConfig 1 2>&1 trace.log
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../scripts/toaxe.py trace.log > trace.axe
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axe check WMO trace.axe
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```
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> cd emulator
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> make CONFIG=TraceGenConfig
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> tracegen.py ./emulator-Top-TraceGenConfig 1 > trace.log
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> toaxe.py trace.log > trace.axe
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> axe check WMO trace.axe
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OK
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```
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### Longer Explanation
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@ -81,7 +85,7 @@ axe check WMO trace.axe
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Suppose we have built the Rocket Chip emulator with the TraceGenConfig configuration as above. Running it using the tracegen.py wrapper script with a few command-line options gives us a random trace:
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```
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> ../scripts/tracegen.py ./emulator-Top-TraceGenConfig 1
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> tracegen.py ./emulator-Top-TraceGenConfig 1
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1: load-req 0x0000000008 #0 @64
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1: store-req 5 0x0000100008 #1 @65
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1: store-req 7 0x0000000010 #2 @66
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@ -106,17 +110,18 @@ Main points:
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- the numeric command-line option sets the random seed;
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- the first number on each line of the trace is the core id;
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- \#N denotes a request-id N;
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- \@T denotes a time T in clock cycles;
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- @T denotes a time T in clock cycles;
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- hex numbers denote addresses;
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- remaining decimal numbers denote values being loaded or stored;
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- the value written by every store is unique (this simplifies trace checking and reasoning);
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- this trace contains only loads, stores and responses, but the generator (and axe) also support LR/SC pairs, atomics, and fences.
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We convert these traces to axe format using the toaxe.py script available in rocket-chip/scripts.
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We convert these traces to axe format using the
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[toaxe.py](https://github.com/ucb-bar/rocket-chip/blob/master/scripts/tracegen%2Bcheck.sh) script available in rocket-chip/scripts.
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```
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> ../scripts/tracegen.py ./emulator-Top-TraceGenConfig 1 2>&1 | ../scripts/toaxe.py -
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> tracegen.py ./emulator-Top-TraceGenConfig 1 | toaxe.py -
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# &M[2] == 0x0000000010
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# &M[0] == 0x0000000008
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# &M[3] == 0x0000000108
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@ -134,89 +139,13 @@ We convert these traces to axe format using the toaxe.py script available in roc
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Main points:
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- Chisel printfs go to stdout, hence the re-direction 2>&1;
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- lines begining # are comments, showing the addresses being used;
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- after @ are the optional begin and end times of the operation.
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Axe traces can be validated using the axe tool (must be downloaded and installed seperately):
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Axe traces can be validated using the [axe](https://github.com/CTSRD-CHERI/axe) tool (must be downloaded and installed seperately):
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```
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> ../scripts/tracegen.py ./emulator-Top-TraceGenConfig 1 2>&1 | ../scripts/toaxe.py -| axe check SC -
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OK
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```
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Axe reports that this trace is valid according to the SC model, i.e. sequential consistency.
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For intensive testing, we can put the above command into a for-loop that changes the seed on each iteration.
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```bash
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#!/bin/bash
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# FILE "isit"
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MODEL=$1
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for I in {1..10000}; do
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OUT=`../scripts/tracegen.py ./emulator-Top-TraceGenConfig $I 2>&1 | ../scripts/toaxe.py - | axe check $MODEL -`
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if [ "$OUT" == "NO" ]; then
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echo Not $MODEL, seed=$I
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exit
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fi
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done
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echo Passed $I tests
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```
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We can now ask: is the memory-subsystem SC?
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```
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> isit SC
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Not SC, seed=13
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```
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We can view the counter-example by running the emulator with seed of 13:
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```
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> ../scripts/tracegen.py ./emulator-Top-TraceGenConfig 13 2>&1 | ../scripts/toaxe.py - | axe check SC -
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NO
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```
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However the resulting trace is rather long. One option is to the adjust the generator's compile-time parameters to produce smaller traces. Here, we pipe the trace through [axe-shrink](https://github.com/CTSRD-CHERI/axe/blob/master/src/axe-shrink.py) which tries to find the smallest subset of the trace the violates the given model.
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```
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> ../scripts/tracegen.py ./emulator-Top-TraceGenConfig 13 | & cat - | ../scripts/toaxe.py - | axe-shrink.py SC -
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Pass 0
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Omitted 258 of 276
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Pass 1
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Omitted 268 of 276
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Pass 2
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Omitted 268 of 276
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0: M[1] := 58 @ 231:
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0: M[2] := 68 @ 244:
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0: { M[2] == 68; M[2] := 76} @ 257:
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1: { M[2] == 76; M[2] := 13} @ 198:
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1: M[1] := 17 @ 237:
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1: { M[2] == 13; M[2] := 19} @ 262:
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0: M[2] == 19 @ 505:543
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0: M[1] == 58 @ 506:508
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```
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One possible explanation for this behavior is that core 1 performs its writes out of order. This kind of reordering is allowed by the SPARC PSO model:
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```
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> ../scripts/tracegen.py ./emulator-Top-TraceGenConfig 13 | & cat - | ../scripts/toaxe.py - | axe check PSO -
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> tracegen.py ./emulator-Top-TraceGenConfig 1 | toaxe.py - | axe check WMO -
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OK
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```
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Now we ask: is the memory-subsystem PSO?
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```
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> isit PSO
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Not PSO, seed=96
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```
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At the time of writing, rocket-chip appears to satisfy WMO
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```
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> isit WMO
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Passed 10000 tests
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```
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This concludes the quick demo.
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Axe reports that this trace is valid according to the WMO model.
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