switch RTC to use TileLink instead of AXI
This commit is contained in:
parent
7f8f138d6a
commit
8e7f18084b
@ -7,62 +7,58 @@ import cde.{Parameters, Field}
|
||||
case object RTCPeriod extends Field[Int]
|
||||
|
||||
class RTC(csr_MTIME: Int)(implicit p: Parameters) extends HtifModule
|
||||
with HasTileLinkParameters
|
||||
with HasAddrMapParameters {
|
||||
val io = new NastiIO
|
||||
val io = new ClientUncachedTileLinkIO
|
||||
|
||||
val addrTable = Vec.tabulate(nCores) { i =>
|
||||
UInt(addrMap(s"conf:csr$i").start + csr_MTIME * csrDataBytes)
|
||||
UInt(addrMap(s"conf:csr$i").start + csr_MTIME * csrDataBytes, p(PAddrBits))
|
||||
}
|
||||
|
||||
val rtc = Reg(init=UInt(0, scrDataBits))
|
||||
val rtc = Reg(init=UInt(0, csrDataBits))
|
||||
val rtc_tick = Counter(p(RTCPeriod)).inc()
|
||||
|
||||
val sending_addr = Reg(init = Bool(false))
|
||||
val sending_data = Reg(init = Bool(false))
|
||||
val sending = Reg(init = Bool(false))
|
||||
val send_acked = Reg(init = Vec.fill(nCores)(Bool(true)))
|
||||
val coreId = Wire(UInt(width = log2Up(nCores)))
|
||||
|
||||
when (rtc_tick) {
|
||||
rtc := rtc + UInt(1)
|
||||
send_acked := Vec.fill(nCores)(Bool(false))
|
||||
sending_addr := Bool(true)
|
||||
sending_data := Bool(true)
|
||||
sending := Bool(true)
|
||||
}
|
||||
|
||||
if (nCores > 1) {
|
||||
val (addr_send_cnt, addr_send_done) = Counter(io.aw.fire(), nCores)
|
||||
val (_, data_send_done) = Counter(io.w.fire(), nCores)
|
||||
val (send_cnt, send_done) = Counter(io.acquire.fire(), nCores)
|
||||
|
||||
when (addr_send_done) { sending_addr := Bool(false) }
|
||||
when (data_send_done) { sending_data := Bool(false) }
|
||||
when (send_done) { sending := Bool(false) }
|
||||
|
||||
coreId := addr_send_cnt
|
||||
coreId := send_cnt
|
||||
} else {
|
||||
when (io.aw.fire()) { sending_addr := Bool(false) }
|
||||
when (io.w.fire()) { sending_data := Bool(false) }
|
||||
when (io.acquire.fire()) { sending := Bool(false) }
|
||||
|
||||
coreId := UInt(0)
|
||||
}
|
||||
|
||||
when (io.b.fire()) { send_acked(io.b.bits.id) := Bool(true) }
|
||||
when (io.grant.fire()) { send_acked(io.grant.bits.client_xact_id) := Bool(true) }
|
||||
|
||||
io.aw.valid := sending_addr
|
||||
io.aw.bits := NastiWriteAddressChannel(
|
||||
id = coreId,
|
||||
addr = addrTable(coreId),
|
||||
size = UInt(log2Up(csrDataBytes)))
|
||||
require(p(MIFMasterTagBits) >= log2Up(nCores))
|
||||
val addr_full = addrTable(coreId)
|
||||
val addr_block = addr_full(p(PAddrBits) - 1, p(CacheBlockOffsetBits))
|
||||
val addr_beat = addr_full(p(CacheBlockOffsetBits) - 1, tlByteAddrBits)
|
||||
val addr_byte = addr_full(tlByteAddrBits - 1, 0)
|
||||
val wmask = Fill(csrDataBytes, UInt(1, 1)) << addr_byte
|
||||
|
||||
io.w.valid := sending_data
|
||||
io.w.bits := NastiWriteDataChannel(data = rtc)
|
||||
io.acquire.valid := sending
|
||||
io.acquire.bits := Put(
|
||||
client_xact_id = coreId,
|
||||
addr_block = addr_block,
|
||||
addr_beat = addr_beat,
|
||||
wmask = wmask,
|
||||
data = Fill(tlDataBytes / csrDataBytes, rtc))
|
||||
io.grant.ready := Bool(true)
|
||||
|
||||
io.b.ready := Bool(true)
|
||||
io.ar.valid := Bool(false)
|
||||
io.r.ready := Bool(false)
|
||||
require(tlClientXactIdBits >= log2Up(nCores))
|
||||
|
||||
assert(!rtc_tick || send_acked.reduce(_ && _),
|
||||
"Not all clocks were updated for rtc tick")
|
||||
|
||||
assert(!io.b.valid || io.b.bits.resp === UInt(0),
|
||||
"RTC received NASTI error response")
|
||||
}
|
||||
|
Loading…
Reference in New Issue
Block a user