riscv/rocket-chip
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fix leaky assert in nbdcache

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Squash of #33.
This commit is contained in:
Christopher Celio 2016-03-31 15:55:22 -07:00 committed by Andrew Waterman
parent adb7eacf6e
commit 1792d01ce1
1 changed files with 2 additions and 1 deletions
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rocket/src/main/scala/nbdcache.scala
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@ -821,7 +821,8 @@ class HellaCache(implicit p: Parameters) extends L1HellaCacheModule()(p) {
assert (!(Reg(next=
(io.cpu.xcpt.ma.ld || io.cpu.xcpt.ma.st || io.cpu.xcpt.pf.ld || io.cpu.xcpt.pf.st)) &&
io.cpu.resp.valid), "DCache exception occurred - cache response not killed.")
s2_valid_masked),
"DCache exception occurred - cache response not killed.")
// tags
def onReset = L1Metadata(UInt(0), ClientMetadata.onReset)