Revert "switch back to Chisel2 for verilog build for now"

This reverts commit 3673365b08.
2016-03-30 19:00:38 -07:00
parent 8e601f26e1
commit e77900f540
1 changed files with 1 additions and 1 deletions
--- a/.travis.yml
+++ b/.travis.yml
@@ -64,7 +64,7 @@ before_install:
  - export CXX=g++-4.8 CC=gcc-4.8

 script:
-  - make vsim-verilog -C regression CONFIG=$CONFIG TORTURE_CONFIG=default
+  - make vsim-verilog -C regression CONFIG=$CONFIG TORTURE_CONFIG=default CHISEL_VERSION=3
  - make fsim-verilog -C regression CONFIG=$CONFIG TORTURE_CONFIG=default
  - make emulator-ndebug -C regression CONFIG=$CONFIG TORTURE_CONFIG=default
  - make emulator-asm-tests   -C regression CONFIG=$CONFIG TORTURE_CONFIG=default