move AtosConverterTest into UnitTestSuite
This commit is contained in:
Howard Mao
parent
d19aaf8d89
commit
ee66da603a
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@ -1,135 +0,0 @@
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package groundtest
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import Chisel._
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import junctions._
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import junctions.StreamUtils._
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import cde.Parameters
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class AtosConverterTestFrontend(implicit p: Parameters) extends NastiModule()(p) {
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val io = new Bundle {
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val nasti = new NastiIO
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val finished = Bool(OUTPUT)
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}
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val n_words = 4
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val test_data = Vec.tabulate(n_words) { i => UInt(i * 48) }
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val (s_idle :: s_waddr :: s_wdata :: s_wresp ::
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s_raddr :: s_rresp :: s_done :: Nil) = Enum(Bits(), 7)
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val state = Reg(init = s_idle)
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when (state === s_idle) { state := s_waddr }
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when (io.nasti.aw.fire()) { state := s_wdata }
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when (io.nasti.w.fire() && io.nasti.w.bits.last) { state := s_wresp }
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when (io.nasti.b.fire()) { state := s_raddr }
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when (io.nasti.ar.fire()) { state := s_rresp }
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when (io.nasti.r.fire() && io.nasti.r.bits.last) { state := s_done }
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val (w_count, w_last) = Counter(io.nasti.w.fire(), n_words)
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io.nasti.aw.valid := (state === s_waddr)
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io.nasti.aw.bits := NastiWriteAddressChannel(
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id = UInt(0),
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addr = UInt(0),
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size = UInt(log2Up(nastiXDataBits / 8)),
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len = UInt(n_words - 1))
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io.nasti.w.valid := (state === s_wdata)
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io.nasti.w.bits := NastiWriteDataChannel(
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data = test_data(w_count),
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last = w_count === UInt(n_words - 1))
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io.nasti.ar.valid := (state === s_raddr)
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io.nasti.ar.bits := NastiReadAddressChannel(
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id = UInt(0),
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addr = UInt(0),
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size = UInt(log2Up(nastiXDataBits / 8)),
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len = UInt(n_words - 1))
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io.nasti.b.ready := (state === s_wresp)
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io.nasti.r.ready := (state === s_rresp)
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io.finished := (state === s_done)
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val (r_count, r_last) = Counter(io.nasti.r.fire(), n_words)
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assert(!io.nasti.r.valid || io.nasti.r.bits.data === test_data(r_count),
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"AtosConverterTest: returned data doesn't match expected")
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}
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class AtosConverterTestBackend(implicit p: Parameters) extends NastiModule()(p) {
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val io = new Bundle {
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val nasti = (new NastiIO).flip
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val finished = Bool(OUTPUT)
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}
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val (s_waddr :: s_wdata :: s_wresp ::
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s_raddr :: s_rresp :: s_done :: Nil) = Enum(Bits(), 6)
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val state = Reg(init = s_waddr)
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val n_words = 4
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val test_data = Reg(Vec(n_words, UInt(width = nastiXDataBits)))
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val req_id = Reg(UInt(width = nastiXIdBits))
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val (w_count, w_last) = Counter(io.nasti.w.fire(), n_words)
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val (r_count, r_last) = Counter(io.nasti.r.fire(), n_words)
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when (io.nasti.aw.fire()) {
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req_id := io.nasti.aw.bits.id
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state := s_wdata
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}
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when (io.nasti.w.fire()) {
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test_data(w_count) := io.nasti.w.bits.data
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when (io.nasti.w.bits.last) { state := s_wresp }
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}
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when (io.nasti.b.fire()) { state := s_raddr }
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when (io.nasti.ar.fire()) {
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req_id := io.nasti.ar.bits.id
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state := s_rresp
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}
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when (io.nasti.r.fire() && io.nasti.r.bits.last) { state := s_done }
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io.nasti.aw.ready := (state === s_waddr)
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io.nasti.w.ready := (state === s_wdata)
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io.nasti.ar.ready := (state === s_raddr)
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io.nasti.b.valid := (state === s_wresp)
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io.nasti.b.bits := NastiWriteResponseChannel(id = req_id)
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io.nasti.r.valid := (state === s_rresp)
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io.nasti.r.bits := NastiReadDataChannel(
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id = req_id,
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data = test_data(r_count),
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last = r_last)
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io.finished := (state === s_done)
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}
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class AtosConverterTest(implicit p: Parameters) extends GroundTest()(p) {
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disablePorts()
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val frontend = Module(new AtosConverterTestFrontend)
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val backend = Module(new AtosConverterTestBackend)
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val fe_ser = Module(new Serializer(new AtosRequest))
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val fe_des = Module(new Deserializer(new AtosResponse))
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val be_des = Module(new Deserializer(new AtosRequest))
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val be_ser = Module(new Serializer(new AtosResponse))
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val client_conv = Module(new AtosClientConverter)
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val manager_conv = Module(new AtosManagerConverter)
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client_conv.io.nasti <> frontend.io.nasti
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fe_ser.io.in <> client_conv.io.atos.req
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client_conv.io.atos.resp <> fe_des.io.out
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be_des.io.in <> fe_ser.io.out
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fe_des.io.in <> be_ser.io.out
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manager_conv.io.atos.req <> be_des.io.out
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be_ser.io.in <> manager_conv.io.atos.resp
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backend.io.nasti <> manager_conv.io.nasti
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io.finished := frontend.io.finished && backend.io.finished
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}
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@ -287,13 +287,141 @@ class TileLinkToSmiConverterTest(implicit p: Parameters) extends UnitTest {
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io.finished := driver.io.finished
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}
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class AtosConverterTestFrontend(implicit p: Parameters) extends NastiModule()(p) {
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val io = new Bundle {
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val nasti = new NastiIO
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val finished = Bool(OUTPUT)
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}
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val n_words = 4
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val test_data = Vec.tabulate(n_words) { i => UInt(i * 48) }
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val (s_idle :: s_waddr :: s_wdata :: s_wresp ::
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s_raddr :: s_rresp :: s_done :: Nil) = Enum(Bits(), 7)
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val state = Reg(init = s_idle)
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when (state === s_idle) { state := s_waddr }
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when (io.nasti.aw.fire()) { state := s_wdata }
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when (io.nasti.w.fire() && io.nasti.w.bits.last) { state := s_wresp }
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when (io.nasti.b.fire()) { state := s_raddr }
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when (io.nasti.ar.fire()) { state := s_rresp }
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when (io.nasti.r.fire() && io.nasti.r.bits.last) { state := s_done }
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val (w_count, w_last) = Counter(io.nasti.w.fire(), n_words)
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io.nasti.aw.valid := (state === s_waddr)
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io.nasti.aw.bits := NastiWriteAddressChannel(
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id = UInt(0),
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addr = UInt(0),
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size = UInt(log2Up(nastiXDataBits / 8)),
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len = UInt(n_words - 1))
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io.nasti.w.valid := (state === s_wdata)
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io.nasti.w.bits := NastiWriteDataChannel(
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data = test_data(w_count),
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last = w_count === UInt(n_words - 1))
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io.nasti.ar.valid := (state === s_raddr)
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io.nasti.ar.bits := NastiReadAddressChannel(
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id = UInt(0),
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addr = UInt(0),
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size = UInt(log2Up(nastiXDataBits / 8)),
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len = UInt(n_words - 1))
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io.nasti.b.ready := (state === s_wresp)
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io.nasti.r.ready := (state === s_rresp)
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io.finished := (state === s_done)
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val (r_count, r_last) = Counter(io.nasti.r.fire(), n_words)
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assert(!io.nasti.r.valid || io.nasti.r.bits.data === test_data(r_count),
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"AtosConverterTest: returned data doesn't match expected")
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}
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class AtosConverterTestBackend(implicit p: Parameters) extends NastiModule()(p) {
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val io = new Bundle {
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val nasti = (new NastiIO).flip
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val finished = Bool(OUTPUT)
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}
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val (s_waddr :: s_wdata :: s_wresp ::
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s_raddr :: s_rresp :: s_done :: Nil) = Enum(Bits(), 6)
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val state = Reg(init = s_waddr)
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val n_words = 4
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val test_data = Reg(Vec(n_words, UInt(width = nastiXDataBits)))
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val req_id = Reg(UInt(width = nastiXIdBits))
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val (w_count, w_last) = Counter(io.nasti.w.fire(), n_words)
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val (r_count, r_last) = Counter(io.nasti.r.fire(), n_words)
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when (io.nasti.aw.fire()) {
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req_id := io.nasti.aw.bits.id
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state := s_wdata
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}
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when (io.nasti.w.fire()) {
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test_data(w_count) := io.nasti.w.bits.data
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when (io.nasti.w.bits.last) { state := s_wresp }
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}
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when (io.nasti.b.fire()) { state := s_raddr }
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when (io.nasti.ar.fire()) {
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req_id := io.nasti.ar.bits.id
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state := s_rresp
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}
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when (io.nasti.r.fire() && io.nasti.r.bits.last) { state := s_done }
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io.nasti.aw.ready := (state === s_waddr)
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io.nasti.w.ready := (state === s_wdata)
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io.nasti.ar.ready := (state === s_raddr)
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io.nasti.b.valid := (state === s_wresp)
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io.nasti.b.bits := NastiWriteResponseChannel(id = req_id)
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io.nasti.r.valid := (state === s_rresp)
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io.nasti.r.bits := NastiReadDataChannel(
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id = req_id,
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data = test_data(r_count),
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last = r_last)
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io.finished := (state === s_done)
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}
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class AtosConverterTest(implicit p: Parameters) extends UnitTest {
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val frontend = Module(new AtosConverterTestFrontend)
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val backend = Module(new AtosConverterTestBackend)
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val fe_ser = Module(new Serializer(new AtosRequest))
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val fe_des = Module(new Deserializer(new AtosResponse))
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val be_des = Module(new Deserializer(new AtosRequest))
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val be_ser = Module(new Serializer(new AtosResponse))
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val client_conv = Module(new AtosClientConverter)
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val manager_conv = Module(new AtosManagerConverter)
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client_conv.io.nasti <> frontend.io.nasti
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fe_ser.io.in <> client_conv.io.atos.req
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client_conv.io.atos.resp <> fe_des.io.out
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be_des.io.in <> fe_ser.io.out
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fe_des.io.in <> be_ser.io.out
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manager_conv.io.atos.req <> be_des.io.out
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be_ser.io.in <> manager_conv.io.atos.resp
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backend.io.nasti <> manager_conv.io.nasti
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io.finished := frontend.io.finished && backend.io.finished
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}
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class UnitTestSuite(implicit p: Parameters) extends GroundTest()(p) {
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disablePorts()
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val tests = Seq(
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Module(new MultiWidthFifoTest),
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Module(new NastiIOHostIOConverterTest),
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Module(new TileLinkToSmiConverterTest))
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Module(new TileLinkToSmiConverterTest),
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Module(new AtosConverterTest))
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val s_idle :: s_start :: s_wait :: Nil = Enum(Bits(), 3)
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val state = Reg(init = s_idle)
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