riscv/rocket-chip
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fix addPendingBitWhenPartialWritemask

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This commit is contained in:
Howard Mao
2016-03-24 19:48:52 -07:00
parent 11bd15432a
commit 7f8f138d6a
1 changed files with 1 additions and 1 deletions
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2
uncore/src/main/scala/cache.scala
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@@ -508,7 +508,7 @@ abstract class L2XactTracker(implicit p: Parameters) extends XactTracker()(p)
def addPendingBitWhenBeatHasPartialWritemask(in: DecoupledIO[AcquireFromSrc]): UInt = {
val a = in.bits
val isPartial = a.wmask() =/= Acquire.fullWriteMask
addPendingBitWhenBeat(in.fire() && isPartial && Bool(ignoresWriteMask), a)
addPendingBitWhenBeat(in.fire() && (isPartial || Bool(ignoresWriteMask)), a)
}
}