LRSC startvation fix: HellaCache generates its own Finish messages again.
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37b9051762
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@ -147,7 +147,8 @@ class IOMSHR(id: Int)(implicit p: Parameters) extends L1HellaCacheModule()(p) {
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val io = new Bundle {
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val req = Decoupled(new HellaCacheReq).flip
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val acquire = Decoupled(new Acquire)
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val grant = Valid(new Grant).flip
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val grant = Valid(new GrantFromSrc).flip
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val finish = Decoupled(new FinishToDst)
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val resp = Decoupled(new HellaCacheResp)
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}
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@ -160,6 +161,11 @@ class IOMSHR(id: Int)(implicit p: Parameters) extends L1HellaCacheModule()(p) {
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val req = Reg(new HellaCacheReq)
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val req_cmd_sc = req.cmd === M_XSC
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val grant_word = Reg(UInt(width = wordBits))
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val fq = Module(new FinishQueue(1))
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fq.io.enq.valid := io.grant.valid && io.grant.bits.requiresAck()
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fq.io.enq.bits := io.grant.bits.makeFinish()
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io.finish <> fq.io.deq
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val storegen = new StoreGen(req.typ, req.addr, req.data, wordBytes)
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val loadgen = new LoadGen(req.typ, req.addr, grant_word, req_cmd_sc, wordBytes)
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@ -168,7 +174,7 @@ class IOMSHR(id: Int)(implicit p: Parameters) extends L1HellaCacheModule()(p) {
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val beat_mask = (storegen.mask << Cat(beat_offset, UInt(0, wordOffBits)))
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val beat_data = Fill(beatWords, storegen.data)
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val s_idle :: s_acquire :: s_grant :: s_resp :: Nil = Enum(Bits(), 4)
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val s_idle :: s_acquire :: s_grant :: s_resp :: s_finish :: Nil = Enum(Bits(), 5)
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val state = Reg(init = s_idle)
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io.req.ready := (state === s_idle)
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@ -223,6 +229,10 @@ class IOMSHR(id: Int)(implicit p: Parameters) extends L1HellaCacheModule()(p) {
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}
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when (io.resp.fire()) {
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state := s_finish
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}
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when (io.finish.fire()) {
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state := s_idle
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}
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}
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@ -243,7 +253,8 @@ class MSHR(id: Int)(implicit p: Parameters) extends L1HellaCacheModule()(p) {
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val meta_read = Decoupled(new L1MetaReadReq)
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val meta_write = Decoupled(new L1MetaWriteReq)
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val replay = Decoupled(new ReplayInternal)
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val mem_grant = Valid(new Grant).flip
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val mem_grant = Valid(new GrantFromSrc).flip
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val mem_finish = Decoupled(new FinishToDst)
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val wb_req = Decoupled(new WritebackReq)
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val probe_rdy = Bool(OUTPUT)
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}
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@ -290,9 +301,9 @@ class MSHR(id: Int)(implicit p: Parameters) extends L1HellaCacheModule()(p) {
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when (state === s_meta_write_req && io.meta_write.ready) {
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state := s_meta_write_resp
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}
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when (state === s_refill_resp) {
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when (io.mem_grant.valid) { new_coh_state := coh_on_grant }
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when (refill_done) { state := s_meta_write_req }
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when (state === s_refill_resp && refill_done) {
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state := s_meta_write_req
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new_coh_state := coh_on_grant
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}
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when (io.mem_req.fire()) { // s_refill_req
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state := s_refill_resp
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@ -329,6 +340,15 @@ class MSHR(id: Int)(implicit p: Parameters) extends L1HellaCacheModule()(p) {
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}
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}
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val fq = Module(new FinishQueue(1))
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val g = io.mem_grant.bits
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val can_finish = state === s_invalid || state === s_refill_req || state === s_refill_resp
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fq.io.enq.valid := io.mem_grant.valid && g.requiresAck() && refill_done
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fq.io.enq.bits := g.makeFinish()
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io.mem_finish.valid := fq.io.deq.valid && can_finish
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fq.io.deq.ready := io.mem_finish.ready && can_finish
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io.mem_finish.bits := fq.io.deq.bits
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io.idx_match := (state =/= s_invalid) && idx_match
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io.refill.way_en := req.way_en
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io.refill.addr := (if(refillCycles > 1) Cat(req_idx, refill_cnt) else req_idx) << rowOffBits
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@ -355,7 +375,7 @@ class MSHR(id: Int)(implicit p: Parameters) extends L1HellaCacheModule()(p) {
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addr_block = Cat(req.old_meta.tag, req_idx))
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io.wb_req.bits.way_en := req.way_en
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io.mem_req.valid := state === s_refill_req
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io.mem_req.valid := state === s_refill_req && fq.io.enq.ready
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io.mem_req.bits := req.old_meta.coh.makeAcquire(
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addr_block = Cat(io.tag, req_idx).toUInt,
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client_xact_id = Bits(id),
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@ -387,7 +407,8 @@ class MSHRFile(implicit p: Parameters) extends L1HellaCacheModule()(p) {
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val meta_read = Decoupled(new L1MetaReadReq)
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val meta_write = Decoupled(new L1MetaWriteReq)
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val replay = Decoupled(new Replay)
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val mem_grant = Valid(new Grant).flip
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val mem_grant = Valid(new GrantFromSrc).flip
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val mem_finish = Decoupled(new FinishToDst)
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val wb_req = Decoupled(new WritebackReq)
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val probe_rdy = Bool(OUTPUT)
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@ -417,6 +438,7 @@ class MSHRFile(implicit p: Parameters) extends L1HellaCacheModule()(p) {
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nMSHRs + nIOMSHRs,
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outerDataBeats,
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(a: Acquire) => a.hasMultibeatData()))
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val mem_finish_arb = Module(new Arbiter(new FinishToDst, nMSHRs + nIOMSHRs))
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val wb_req_arb = Module(new Arbiter(new WritebackReq, nMSHRs))
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val replay_arb = Module(new Arbiter(new ReplayInternal, nMSHRs))
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val alloc_arb = Module(new Arbiter(Bool(), nMSHRs))
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@ -445,6 +467,7 @@ class MSHRFile(implicit p: Parameters) extends L1HellaCacheModule()(p) {
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meta_read_arb.io.in(i) <> mshr.io.meta_read
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meta_write_arb.io.in(i) <> mshr.io.meta_write
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mem_req_arb.io.in(i) <> mshr.io.mem_req
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mem_finish_arb.io.in(i) <> mshr.io.mem_finish
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wb_req_arb.io.in(i) <> mshr.io.wb_req
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replay_arb.io.in(i) <> mshr.io.replay
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@ -466,6 +489,7 @@ class MSHRFile(implicit p: Parameters) extends L1HellaCacheModule()(p) {
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io.meta_read <> meta_read_arb.io.out
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io.meta_write <> meta_write_arb.io.out
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io.mem_req <> mem_req_arb.io.out
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io.mem_finish <> mem_finish_arb.io.out
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io.wb_req <> wb_req_arb.io.out
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val mmio_alloc_arb = Module(new Arbiter(Bool(), nIOMSHRs))
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@ -484,6 +508,7 @@ class MSHRFile(implicit p: Parameters) extends L1HellaCacheModule()(p) {
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mmio_rdy = mmio_rdy || mshr.io.req.ready
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mem_req_arb.io.in(id) <> mshr.io.acquire
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mem_finish_arb.io.in(id) <> mshr.io.finish
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mshr.io.grant.bits := io.mem_grant.bits
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mshr.io.grant.valid := io.mem_grant.valid &&
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@ -981,6 +1006,7 @@ class HellaCache(implicit p: Parameters) extends L1HellaCacheModule()(p) {
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writeArb.io.in(1).bits.data := narrow_grant.bits.data(encRowBits-1,0)
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data.io.read <> readArb.io.out
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readArb.io.out.ready := !narrow_grant.valid || narrow_grant.ready // insert bubble if refill gets blocked
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io.mem.finish <> mshrs.io.mem_finish
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// writebacks
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val wbArb = Module(new Arbiter(new WritebackReq, 2))
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