separate btb response mask from the frontend mask
It is now the job of the pipeline to monitor the frontend's valid mask (of instructions) and the BTB's suggested valid mask (based on the prediction it makes). Some processors may want to ignore or override the BTB's prediction and thus can supply their own instruction mask.
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@ -115,8 +115,8 @@ class RASUpdate(implicit p: Parameters) extends BtbBundle()(p) {
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// - "bridx" is the low-order PC bits of the predicted branch (after
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// shifting off the lowest log(inst_bytes) bits off).
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// - "resp.mask" provides a mask of valid instructions (instructions are
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// masked off by the predicted taken branch).
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// - "mask" provides a mask of valid instructions (instructions are
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// masked off by the predicted taken branch from the BTB).
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class BTBResp(implicit p: Parameters) extends BtbBundle()(p) {
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val taken = Bool()
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val mask = Bits(width = fetchWidth)
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@ -131,7 +131,7 @@ class Frontend(implicit p: Parameters) extends CoreModule()(p) with HasL1CachePa
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val all_ones = UInt((1 << (fetchWidth+1))-1)
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val msk_pc = if (fetchWidth == 1) all_ones else all_ones << s2_pc(log2Up(fetchWidth) -1+2,2)
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io.cpu.resp.bits.mask := Mux(s2_btb_resp_valid, msk_pc & s2_btb_resp_bits.mask, msk_pc)
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io.cpu.resp.bits.mask := msk_pc
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io.cpu.resp.bits.xcpt_if := s2_xcpt_if
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io.cpu.btb_resp.valid := s2_btb_resp_valid
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