riscv/rocket-chip
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switch back to Chisel2 for verilog build for now

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Howard Mao 2016-03-28 13:26:04 -07:00
parent 265a82427e
commit 3673365b08
1 changed files with 1 additions and 1 deletions
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.travis.yml
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@ -64,7 +64,7 @@ before_install:
- export CXX=g++-4.8 CC=gcc-4.8
script:
- make vsim-verilog -C regression CONFIG=$CONFIG TORTURE_CONFIG=default CHISEL_VERSION=3
- make vsim-verilog -C regression CONFIG=$CONFIG TORTURE_CONFIG=default
- make fsim-verilog -C regression CONFIG=$CONFIG TORTURE_CONFIG=default
- make emulator-ndebug -C regression CONFIG=$CONFIG TORTURE_CONFIG=default
- make emulator-asm-tests -C regression CONFIG=$CONFIG TORTURE_CONFIG=default