riscv/rocket-chip
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don't connect unnecessary wires in regression test

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This commit is contained in:
Howard Mao 2016-04-05 15:05:36 -07:00
parent 55df7d97cc
commit d5153bf42e
1 changed files with 0 additions and 4 deletions
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4
groundtest/src/main/scala/regression.scala
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@ -453,10 +453,6 @@ class RegressionTest(implicit p: Parameters) extends GroundTest()(p) {
regress.cache.req.ready := io.cache.req.ready && me
regress.cache.resp.valid := io.cache.resp.valid && me
regress.cache.resp.bits := io.cache.resp.bits
regress.cache.xcpt := io.cache.xcpt
regress.cache.ordered := io.cache.ordered
regress.cache.replay_next.valid := io.cache.replay_next.valid && me
regress.cache.replay_next.bits := io.cache.replay_next.bits
}
val cur_regression = regressIOs(regress_idx)