NASTI to SMI converter test should also test TL to NASTI conversion
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@ -198,9 +198,9 @@ class MultiWidthFifoTest extends UnitTest {
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"Big to Little count incorrect")
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}
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class SmiIONastiIOConverterTestDriver(implicit p: Parameters) extends Module {
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class TileLinkToSmiConverterTestDriver(implicit p: Parameters) extends Module {
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val io = new Bundle {
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val nasti = new NastiIO
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val mem = new ClientUncachedTileLinkIO
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val start = Bool(INPUT)
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val finished = Bool(OUTPUT)
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}
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@ -210,69 +210,79 @@ class SmiIONastiIOConverterTestDriver(implicit p: Parameters) extends Module {
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val addr = Cat(count, UInt(0, 2))
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val data = Fill(4, count)
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val (s_idle :: s_waddr :: s_wdata :: s_wresp :: s_raddr :: s_rresp ::
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s_finished :: Nil) = Enum(Bits(), 7)
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val (s_idle :: s_wreq :: s_wresp :: s_rreq :: s_rresp ::
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s_finished :: Nil) = Enum(Bits(), 6)
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val state = Reg(init = s_idle)
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when (state === s_idle && io.start) { state := s_waddr }
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when (io.nasti.aw.fire()) { state := s_wdata }
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when (io.nasti.w.fire()) { state := s_wresp }
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when (io.nasti.b.fire()) {
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when (state === s_idle && io.start) { state := s_wreq }
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when (state === s_wreq && io.mem.acquire.ready) { state := s_wresp }
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when (state === s_wresp && io.mem.grant.valid) {
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count := count + UInt(1)
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when (count === UInt(nChecks - 1)) {
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state := s_raddr
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state := s_rreq
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} .otherwise {
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state := s_waddr
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state := s_wreq
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}
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}
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when (io.nasti.ar.fire()) { state := s_rresp }
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when (io.nasti.r.fire()) {
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when (state === s_rreq && io.mem.acquire.ready) { state := s_rresp }
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when (state === s_rresp && io.mem.grant.valid) {
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count := count + UInt(1)
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when (count === UInt(nChecks - 1)) {
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state := s_finished
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} .otherwise {
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state := s_raddr
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state := s_rreq
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}
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}
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io.nasti.aw.valid := (state === s_waddr)
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io.nasti.aw.bits := NastiWriteAddressChannel(
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id = UInt(0),
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addr = addr,
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size = UInt("b010"))
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val blockOffsetBits = p(CacheBlockOffsetBits)
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val byteAddrBits = log2Up(p(TLKey(p(TLId))).writeMaskBits)
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io.nasti.w.valid := (state === s_wdata)
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io.nasti.w.bits := NastiWriteDataChannel(
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data = Mux(count(0), data << UInt(32), data)
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)
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io.mem.acquire.valid := (state === s_wreq) || (state === s_rreq)
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io.mem.acquire.bits := Mux(state === s_wreq,
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Put(
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client_xact_id = UInt(0),
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addr_block = addr >> UInt(blockOffsetBits),
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addr_beat = addr(blockOffsetBits - 1, byteAddrBits),
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data = Mux(count(0), data << UInt(32), data),
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wmask = FillInterleaved(4, UIntToOH(count(0)))),
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Get(
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client_xact_id = UInt(0),
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addr_block = addr >> UInt(blockOffsetBits),
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addr_beat = addr(blockOffsetBits - 1, byteAddrBits),
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addr_byte = addr(byteAddrBits - 1, 0),
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operand_size = MT_W,
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alloc = Bool(false)))
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io.mem.grant.ready := (state === s_wresp) || (state === s_rresp)
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io.nasti.b.ready := (state === s_wresp)
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io.nasti.ar.valid := (state === s_raddr)
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io.nasti.ar.bits := NastiReadAddressChannel(
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id = UInt(0),
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addr = addr,
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size = UInt("b010"))
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io.nasti.r.ready := (state === s_rresp)
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assert(!io.nasti.r.valid ||
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assert(!io.mem.grant.valid || !io.mem.grant.bits.hasData() ||
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Mux(count(0),
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io.nasti.r.bits.data(63, 32) === data,
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io.nasti.r.bits.data(31, 0) === data),
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io.mem.grant.bits.data(63, 32) === data,
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io.mem.grant.bits.data(31, 0) === data),
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"Test Driver got incorrect data")
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io.finished := (state === s_finished)
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}
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class SmiIONastiIOConverterTest(implicit p: Parameters) extends UnitTest {
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val smimem = Module(new SmiMem(32, 64))
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val conv = Module(new SmiIONastiIOConverter(32, 6))
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val driver = Module(new SmiIONastiIOConverterTestDriver)
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class TileLinkToSmiConverterTest(implicit p: Parameters) extends UnitTest {
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val outermostParams = p.alterPartial({ case TLId => "Outermost" })
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conv.io.nasti <> driver.io.nasti
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smimem.io <> conv.io.smi
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val smimem = Module(new SmiMem(32, 64))
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val conv1 = Module(new NastiIOTileLinkIOConverter()(outermostParams))
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val conv2 = Module(new SmiIONastiIOConverter(32, 6))
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val driver = Module(new TileLinkToSmiConverterTestDriver()(outermostParams))
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def decoupledNastiConnect(outer: NastiIO, inner: NastiIO) {
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outer.ar <> Queue(inner.ar)
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outer.aw <> Queue(inner.aw)
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outer.w <> Queue(inner.w)
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inner.r <> Queue(outer.r)
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inner.b <> Queue(outer.b)
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}
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conv1.io.tl <> driver.io.mem
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decoupledNastiConnect(conv2.io.nasti, conv1.io.nasti)
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smimem.io <> conv2.io.smi
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driver.io.start := io.start
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io.finished := driver.io.finished
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}
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@ -283,7 +293,7 @@ class UnitTestSuite(implicit p: Parameters) extends GroundTest()(p) {
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val tests = Seq(
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Module(new MultiWidthFifoTest),
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Module(new NastiIOHostIOConverterTest),
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Module(new SmiIONastiIOConverterTest))
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Module(new TileLinkToSmiConverterTest))
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val s_idle :: s_start :: s_wait :: Nil = Enum(Bits(), 3)
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val state = Reg(init = s_idle)
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