fix AXI -> TL converter
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@ -584,13 +584,7 @@ class TileLinkIONastiIOConverter(implicit p: Parameters) extends TLModule()(p)
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def nasti_wmask(aw: NastiWriteAddressChannel, w: NastiWriteDataChannel): UInt = {
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val base = w.strb & size_mask(aw.size)
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val addr_byte = nasti_addr_byte(aw)
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base << addr_byte
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}
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def nasti_wdata(aw: NastiWriteAddressChannel, w: NastiWriteDataChannel): UInt = {
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val base = w.data & FillInterleaved(8, size_mask(aw.size))
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val addr_byte = nasti_addr_byte(aw)
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base << Cat(addr_byte, UInt(0, 3))
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w.strb & (size_mask(aw.size) << addr_byte)
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}
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def tl_last(gnt: GrantMetadata): Bool =
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@ -645,7 +639,7 @@ class TileLinkIONastiIOConverter(implicit p: Parameters) extends TLModule()(p)
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client_xact_id = aw_req.id,
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addr_block = nasti_addr_block(aw_req),
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addr_beat = nasti_addr_beat(aw_req),
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data = nasti_wdata(aw_req, io.nasti.w.bits),
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data = io.nasti.w.bits.data,
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wmask = nasti_wmask(aw_req, io.nasti.w.bits)))
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io.tl.acquire.bits := Mux(state === s_put, put_acquire, get_acquire)
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@ -655,19 +649,7 @@ class TileLinkIONastiIOConverter(implicit p: Parameters) extends TLModule()(p)
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io.nasti.aw.ready := (state === s_idle && !io.nasti.ar.valid)
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io.nasti.w.ready := (state === s_put && io.tl.acquire.ready)
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val acq = io.tl.acquire.bits
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val nXacts = tlMaxClientXacts * tlMaxClientsPerPort
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val get_align = Reg(Vec(nXacts, UInt(width = tlByteAddrBits)))
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val is_narrow_get = acq.a_type === Acquire.getType
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when (io.tl.acquire.fire() && is_narrow_get) {
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get_align(acq.client_xact_id) := acq.addr_byte()
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}
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def tl_data(gnt: Grant): UInt =
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Mux(gnt.g_type === Grant.getDataBeatType,
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gnt.data >> Cat(get_align(gnt.client_xact_id), UInt(0, 3)),
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gnt.data)
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io.nasti.b.valid := io.tl.grant.valid && tl_b_grant(io.tl.grant.bits)
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io.nasti.b.bits := NastiWriteResponseChannel(
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@ -676,7 +658,7 @@ class TileLinkIONastiIOConverter(implicit p: Parameters) extends TLModule()(p)
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io.nasti.r.valid := io.tl.grant.valid && !tl_b_grant(io.tl.grant.bits)
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io.nasti.r.bits := NastiReadDataChannel(
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id = io.tl.grant.bits.client_xact_id,
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data = tl_data(io.tl.grant.bits),
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data = io.tl.grant.bits.data,
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last = tl_last(io.tl.grant.bits))
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io.tl.grant.ready := Mux(tl_b_grant(io.tl.grant.bits),
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