riscv/rocket-chip
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  • d1c83ccda0 change Tile interface to allow arbitrary number of cached and uncached channels Howard Mao 2016-06-13 16:18:38 -07:00
  • 4a8e6c773a Fix +verbose flag for verilator Andrew Waterman 2016-06-17 21:09:08 -07:00
  • 60bddddfe6 Merge sptbr and sasid Andrew Waterman 2016-06-17 18:29:05 -07:00
  • 719fffff40 make sure updates from irel and iacq gated by tracker allocation Howard Mao 2016-06-17 16:07:47 -07:00
  • b75b6fdcda make sure no-data voluntary releases get tracked Howard Mao 2016-06-17 15:31:40 -07:00
  • ebe95fa827 fix wmask buffer clearing in L2 agents Howard Mao 2016-06-16 15:15:36 -07:00
  • aba13cee7f fix BRAM slave so that it can correctly take all TileLink requests Howard Mao 2016-06-15 20:06:13 -07:00
  • e716661637 make sure merged no-alloc put still allocs if original put allocs Howard Mao 2016-06-14 17:33:12 -07:00
  • 7e43b1d889 fix mistaken dequeueing from roq in TileLink unwrapper Howard Mao 2016-06-09 16:03:29 -07:00
  • 2789e60b6b fix ignt_q logic Howard Mao 2016-06-14 16:07:02 -07:00
  • 16bfbda3c9 Refactor the TransactionTracker logic in all the L2 TileLink Managers. Henry Cook 2016-04-04 22:17:11 -07:00
  • 181b11bf20 allow Comparator to disable prefetches (for testing BroadcastHub) Howard Mao 2016-06-16 15:14:02 -07:00
  • a43a93b55c add BRAMSlave unittest Howard Mao 2016-06-15 20:05:49 -07:00
  • 25ade44fe3 Don't build the Verilator man pages (#141) Palmer Dabbelt 2016-06-16 10:13:21 -07:00
  • ba35712f08 Merge pull request #140 from ucb-bar/verilator Colin Schmidt 2016-06-15 16:25:07 -07:00
  • 0b4c8e9af7 Add D-mode single-step support Andrew Waterman 2016-06-15 16:21:24 -07:00
  • 2d2096e509 Add smaller ROM/RAM for 32-bit debug (#60) mwachs5 2016-06-15 15:07:43 -07:00
  • 68ba33369b Default to Chisel 3 Palmer Dabbelt 2016-06-14 11:42:29 -07:00
  • e617bb8aa8 Start testing Chisel 3 in Travis Palmer Dabbelt 2016-06-14 11:42:25 -07:00
  • f6432395cb Allow the regressions to run more than once Palmer Dabbelt 2016-06-14 21:20:19 -07:00
  • 1525b4717e Install Verilator when building the emulator Palmer Dabbelt 2016-06-14 11:42:19 -07:00
  • 1c2c9f8ed1 bump rocket to fix RoccExampleConfig Colin Schmidt 2016-06-14 17:01:39 -07:00
  • 377de06b72 fix comparator Chisel2 compilation issue Howard Mao 2016-06-14 18:36:38 -07:00
  • b7c0d0cb4d test both cached and uncached cases in MixedAllocPutRegression Howard Mao 2016-06-14 17:01:18 -07:00
  • e3816d5fc7 set invalidate_lr in other rocc examples (#47) Colin Schmidt 2016-06-14 16:59:37 -07:00
  • 571b5b2093 Prevent sbt from running multiple times in emulator Palmer Dabbelt 2016-06-14 11:39:03 -07:00
  • 3ce8dbb6e5 fix make error mixing implicit and normal rules Yunsup Lee 2016-06-10 17:46:45 -07:00
  • 1074c9fe6d change the way regression IOs are assigned Howard Mao 2016-06-14 11:05:18 -07:00
  • e284257052 fully disable the cache when not using it in regression tests Howard Mao 2016-06-14 10:40:52 -07:00
  • 3e105eb352 make sure MixedAllocPutRegression uses a block that hasn't been cached already Howard Mao 2016-06-13 18:17:48 -07:00
  • fe8d81958f fix groundtests to fit new way of parameterizing TileLink clients Howard Mao 2016-06-13 16:17:11 -07:00
  • a921458758 add a regression test for no-alloc Put following an alloc Put Howard Mao 2016-06-13 16:16:26 -07:00
  • e3b4b55836 Refactor breakpoints and support range comparison (currently disabled) Andrew Waterman 2016-06-10 19:55:58 -07:00
  • 82cef6fa7b Make a TileLink to Smi converter availiable to users (#136) Palmer Dabbelt 2016-06-10 18:49:17 -07:00
  • 0c695d8e83 Use the new TileLink to Smi converter (#10) Palmer Dabbelt 2016-06-10 14:04:48 -07:00
  • e5cfc2dac1 Add a Smi to TileLink converter (#59) Palmer Dabbelt 2016-06-10 14:04:28 -07:00
  • b79db89c03 Update breakpoint spec Andrew Waterman 2016-06-09 19:08:24 -07:00
  • c8c7246cce Update breakpoint spec Andrew Waterman 2016-06-09 19:07:10 -07:00
  • 2c325151bf pass invalidate_lr through simple cache interface (#45) Colin Schmidt 2016-06-09 17:22:36 -07:00
  • 70d92995df TestConfigs: add comparator config Wesley W. Terpstra 2016-06-06 10:48:25 -07:00
  • 3e51a8bb7a submodules: include new ComparatorTile Wesley W. Terpstra 2016-06-09 14:43:36 -07:00
  • 1679cf4764 fix groundtest tilelink xacts Howard Mao 2016-06-08 19:59:35 -07:00
  • cee0cf345e [debug] Update Debug ROM contents to write F..F to RAM in case of exception Megan Wachs 2016-06-09 10:30:23 -07:00
  • 5562241a50 comparator: a new TileLink stress-tester Wesley W. Terpstra 2016-06-03 17:12:12 -07:00
  • 586c1079d0 Fix D$ for set size > page size Andrew Waterman 2016-06-09 13:02:28 -07:00
  • dca55a2b35 Respect breakpoint privilege settings Andrew Waterman 2016-06-09 12:41:52 -07:00
  • c85ea7b987 Set badaddr on breakpoints Andrew Waterman 2016-06-09 12:33:43 -07:00
  • 4cd77cef10 Make dcsr.halt writable Andrew Waterman 2016-06-09 12:29:26 -07:00
  • 8516e38eb2 remove implicit modulo addressing in FPU (#44) Colin Schmidt 2016-06-09 11:33:33 -07:00
  • a1ebc73477 tilelink: don't accidentally make a malformed union Wesley W. Terpstra 2016-06-08 16:15:51 -07:00
  • 31b72625aa ahb: allow no-ops to progress also when a slave is !hready Wesley W. Terpstra 2016-06-08 13:11:12 -07:00
  • 7014eef339 ahb: fix bugs found using comparatortest Wesley W. Terpstra 2016-06-08 11:19:22 -07:00
  • 40b6e44816 name resetSignal parameter to tile constructor Colin Schmidt 2016-06-06 10:43:25 -07:00
  • 9e86b9efc9 Add provisional breakpoint support Andrew Waterman 2016-06-08 20:21:21 -07:00
  • 73ed4ea07b grammar Scott Johnson 2016-06-07 21:52:39 -05:00
  • 93c1b17b52 [debug] Remove erroneous buffer on SB read data (#56) mwachs5 2016-06-08 20:31:13 -07:00
  • e3c17b5f74 Add provisional breakpoint support Andrew Waterman 2016-06-08 20:19:52 -07:00
  • 21feeb4a4f have multiple outstanding requests in CacheFillTest Howard Mao 2016-06-08 19:53:42 -07:00
  • ed9fcea7f8 hasti: correct fix to locking Wesley W. Terpstra 2016-06-08 14:35:22 -07:00
  • ad4e4f19be Revert "Don't rely on Mux1H output when no inputs are hot" Wesley W. Terpstra 2016-06-08 13:39:22 -07:00
  • 3393d4362b hasti: fix test SRAM depth Wesley W. Terpstra 2016-06-08 13:25:11 -07:00
  • 65b62a9e5f unbreak the emulator Howard Mao 2016-06-08 13:47:44 -07:00
  • 40ab0a7960 fix TL width adapter and make it easier to switch inner data width Howard Mao 2016-06-08 10:16:04 -07:00
  • a809a1712a make sure clocks and reset signals get intialized properly Howard Mao 2016-06-08 10:03:53 -07:00
  • 5151570894 Fix valid signal for multibeat grants Albert Ou 2016-06-08 15:13:39 -07:00
  • 0969be8804 Revert "make sure SlowIO clock divider is initialized on reset" Howard Mao 2016-06-08 13:45:30 -07:00
  • 636a46c052 make sure SlowIO clock divider is initialized on reset Howard Mao 2016-06-08 10:02:21 -07:00
  • f421e2ab11 fix TileLinkWidthAdapter Howard Mao 2016-06-08 09:58:23 -07:00
  • 99b257316e replace emulator with verilator for chisel3 Donggyu Kim 2016-06-08 01:39:40 -07:00
  • 08e53a00f0 bump cde for better match failure stack trace Howard Mao 2016-06-07 16:15:10 -07:00
  • 2cd897e240 Revert "include the unmatched field in CDEMatchError" Howard Mao 2016-06-07 16:13:01 -07:00
  • 324cabc494 tilelink: wmask was double the width it should be Wesley W. Terpstra 2016-06-07 14:04:01 -07:00
  • 8db27a36c4 fix Tile reset power on behavior Howard Mao 2016-06-07 11:06:25 -07:00
  • e6c4372332 Fix "make run-asm-tests" for Chisel 3 Palmer Dabbelt 2016-06-06 15:02:54 -07:00
  • 2c17f828b6 bump chisel and rocket Andrew Waterman 2016-06-06 21:24:55 -07:00
  • 5495705acf Configs: enable AHB for FPGAs Wesley W. Terpstra 2016-06-01 16:18:42 -07:00
  • ef27cc3a33 RocketChip: handle atomics only if needed Wesley W. Terpstra 2016-06-01 16:09:25 -07:00
  • 3e0ec855cf RocketChip: add ahb mem interface Wesley W. Terpstra 2016-06-01 15:41:58 -07:00
  • d2b505f2d2 RocketChip: rename mem to mem_axi in preparation for new bus type Wesley W. Terpstra 2016-06-01 15:33:24 -07:00
  • 2086c0d603 Configs: add a parameter to control the memory subsystem interface Wesley W. Terpstra 2016-06-01 15:00:48 -07:00
  • 2ddada1732 ahb: add mmio_ahb option Wesley W. Terpstra 2016-05-26 14:49:27 -07:00
  • 31f1dcaf84 ahb: rename mmio outputs to mmio_axi Wesley W. Terpstra 2016-05-26 14:21:54 -07:00
  • 7a24527448 ahb: make MMIO channels specifiy bus type (we will have more than one bridge) Wesley W. Terpstra 2016-05-26 14:14:56 -07:00
  • f3a557b67b ahb: AHB parameters should be site specific Wesley W. Terpstra 2016-05-24 15:59:59 -07:00
  • 4f2e2480a8 When exceptions occur in D-mode, set pc=0x808, not 0x800 Andrew Waterman 2016-06-06 20:57:22 -07:00
  • 172c4f25f4 bump groundtest and uncore Howard Mao 2016-06-06 11:23:32 -07:00
  • f44778fa56 make sure Cached generator comparison truncates to correct size Howard Mao 2016-06-06 17:45:04 -07:00
  • ff2937a788 include the unmatched field in CDEMatchError Howard Mao 2016-06-06 11:23:20 -07:00
  • 022503748e make Memtest generators more configurable Howard Mao 2016-06-06 09:44:09 -07:00
  • 2163ebfca3 use a generic Nasti memory driver for unit tests Howard Mao 2016-06-06 09:43:39 -07:00
  • 2d66ac93d3 make sure HastiRAM cuts off the correct number of bits for word address Howard Mao 2016-06-02 09:04:30 -07:00
  • d24c87f8ba Update PLIC/PRCI address map (#124) Andrew Waterman 2016-06-06 04:51:55 -07:00
  • dd85f2410f Avoid need for cloneType Andrew Waterman 2016-06-05 23:47:56 -07:00
  • 631e3e2dd9 Make PRCI a singleton, not per-tile Andrew Waterman 2016-06-05 23:06:21 -07:00
  • be7500e4a9 Update PLIC addr map Andrew Waterman 2016-06-05 20:33:51 -07:00
  • b832689642 Correct Debug ROM contents Megan Wachs 2016-06-03 18:26:05 -07:00
  • 605fb5b92f [debug]: fix issue with subword select logic Megan Wachs 2016-06-03 15:45:20 -07:00
  • 3e8322816b Correct DMINFO Fields Megan Wachs 2016-06-03 10:48:01 -07:00
  • 7e550ab07c [debug] rocket: fix for issue 121, correct debug ROM and stall logic Megan Wachs 2016-06-02 18:35:17 -07:00
  • ece3ab9c3d Refactor AddrMap and its usage (#122) Andrew Waterman 2016-06-03 17:29:05 -07:00