fix TileLinkWidthAdapter
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parent
324cabc494
commit
f421e2ab11
@ -756,7 +756,7 @@ object TileLinkWidthAdapter {
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widener.io.in <> in
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out <> widener.io.out
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} else if (out.tlDataBits < in.tlDataBits) {
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val narrower = Module(new TileLinkIOWidener(in.p(TLId), out.p(TLId)))
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val narrower = Module(new TileLinkIONarrower(in.p(TLId), out.p(TLId)))
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narrower.io.in <> in
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out <> narrower.io.out
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} else {
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@ -961,9 +961,9 @@ class TileLinkIONarrower(innerTLId: String, outerTLId: String)
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val outerMaxClients = outerParams.maxClientsPerPort
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val outerIdBits = log2Up(outerParams.maxClientXacts * outerMaxClients)
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require(outerDataBeats >= innerDataBeats)
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require(outerDataBeats > innerDataBeats)
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require(outerDataBeats % innerDataBeats == 0)
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require(outerDataBits <= innerDataBits)
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require(outerDataBits < innerDataBits)
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require(outerDataBits * outerDataBeats == innerDataBits * innerDataBeats)
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val factor = outerDataBeats / innerDataBeats
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@ -973,166 +973,164 @@ class TileLinkIONarrower(innerTLId: String, outerTLId: String)
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val out = new ClientUncachedTileLinkIO()(p.alterPartial({case TLId => outerTLId}))
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}
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if (factor > 1) {
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val iacq = io.in.acquire.bits
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val ognt = io.out.grant.bits
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val iacq = io.in.acquire.bits
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val ognt = io.out.grant.bits
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val stretch = iacq.a_type === Acquire.putBlockType
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val shrink = iacq.a_type === Acquire.getBlockType
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val smallput = iacq.a_type === Acquire.putType
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val smallget = iacq.a_type === Acquire.getType
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val stretch = iacq.a_type === Acquire.putBlockType
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val shrink = iacq.a_type === Acquire.getBlockType
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val smallput = iacq.a_type === Acquire.putType
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val smallget = iacq.a_type === Acquire.getType
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val acq_data_buffer = Reg(UInt(width = innerDataBits))
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val acq_wmask_buffer = Reg(UInt(width = innerWriteMaskBits))
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val acq_client_id = Reg(iacq.client_xact_id)
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val acq_addr_block = Reg(iacq.addr_block)
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val acq_addr_beat = Reg(iacq.addr_beat)
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val oacq_ctr = Counter(factor)
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val acq_data_buffer = Reg(UInt(width = innerDataBits))
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val acq_wmask_buffer = Reg(UInt(width = innerWriteMaskBits))
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val acq_client_id = Reg(iacq.client_xact_id)
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val acq_addr_block = Reg(iacq.addr_block)
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val acq_addr_beat = Reg(iacq.addr_beat)
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val oacq_ctr = Counter(factor)
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val outer_beat_addr = iacq.full_addr()(outerBlockOffset - 1, outerByteAddrBits)
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val outer_byte_addr = iacq.full_addr()(outerByteAddrBits - 1, 0)
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val outer_beat_addr = iacq.full_addr()(outerBlockOffset - 1, outerByteAddrBits)
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val outer_byte_addr = iacq.full_addr()(outerByteAddrBits - 1, 0)
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val mask_chunks = Vec.tabulate(factor) { i =>
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val lsb = i * outerWriteMaskBits
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val msb = (i + 1) * outerWriteMaskBits - 1
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iacq.wmask()(msb, lsb)
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val mask_chunks = Vec.tabulate(factor) { i =>
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val lsb = i * outerWriteMaskBits
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val msb = (i + 1) * outerWriteMaskBits - 1
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iacq.wmask()(msb, lsb)
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}
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val data_chunks = Vec.tabulate(factor) { i =>
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val lsb = i * outerDataBits
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val msb = (i + 1) * outerDataBits - 1
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iacq.data(msb, lsb)
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}
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val beat_sel = Cat(mask_chunks.map(mask => mask.orR).reverse)
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val smallput_data = Mux1H(beat_sel, data_chunks)
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val smallput_wmask = Mux1H(beat_sel, mask_chunks)
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val smallput_beat = Cat(iacq.addr_beat, PriorityEncoder(beat_sel))
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assert(!io.in.acquire.valid || !smallput || PopCount(beat_sel) <= UInt(1),
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"Can't perform Put wider than outer width")
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val read_size_ok = MuxLookup(iacq.op_size(), Bool(false), Seq(
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MT_B -> Bool(true),
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MT_BU -> Bool(true),
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MT_H -> Bool(outerDataBits >= 16),
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MT_HU -> Bool(outerDataBits >= 16),
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MT_W -> Bool(outerDataBits >= 32),
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MT_WU -> Bool(outerDataBits >= 32),
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MT_D -> Bool(outerDataBits >= 64),
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MT_Q -> Bool(false)))
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assert(!io.in.acquire.valid || !smallget || read_size_ok,
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"Can't perform Get wider than outer width")
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val outerConfig = p.alterPartial({ case TLId => outerTLId })
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val innerConfig = p.alterPartial({ case TLId => innerTLId })
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val get_block_acquire = GetBlock(
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client_xact_id = iacq.client_xact_id,
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addr_block = iacq.addr_block,
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alloc = iacq.allocate())(outerConfig)
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val put_block_acquire = PutBlock(
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client_xact_id = acq_client_id,
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addr_block = acq_addr_block,
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addr_beat = if (factor > 1)
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Cat(acq_addr_beat, oacq_ctr.value)
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else acq_addr_beat,
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data = acq_data_buffer(outerDataBits - 1, 0),
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wmask = acq_wmask_buffer(outerWriteMaskBits - 1, 0))(outerConfig)
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val get_acquire = Get(
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client_xact_id = iacq.client_xact_id,
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addr_block = iacq.addr_block,
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addr_beat = outer_beat_addr,
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addr_byte = outer_byte_addr,
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operand_size = iacq.op_size(),
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alloc = iacq.allocate())(outerConfig)
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val put_acquire = Put(
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client_xact_id = iacq.client_xact_id,
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addr_block = iacq.addr_block,
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addr_beat = smallput_beat,
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data = smallput_data,
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wmask = Some(smallput_wmask))(outerConfig)
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val sending_put = Reg(init = Bool(false))
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val pass_valid = io.in.acquire.valid && !stretch
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io.out.acquire.bits := MuxBundle(Wire(io.out.acquire.bits, init=iacq), Seq(
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(sending_put, put_block_acquire),
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(shrink, get_block_acquire),
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(smallput, put_acquire),
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(smallget, get_acquire)))
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io.out.acquire.valid := sending_put || pass_valid
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io.in.acquire.ready := !sending_put && (stretch || io.out.acquire.ready)
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when (io.in.acquire.fire() && stretch) {
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acq_data_buffer := iacq.data
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acq_wmask_buffer := iacq.wmask()
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acq_client_id := iacq.client_xact_id
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acq_addr_block := iacq.addr_block
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acq_addr_beat := iacq.addr_beat
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sending_put := Bool(true)
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}
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when (sending_put && io.out.acquire.ready) {
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acq_data_buffer := acq_data_buffer >> outerDataBits
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acq_wmask_buffer := acq_wmask_buffer >> outerWriteMaskBits
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when (oacq_ctr.inc()) { sending_put := Bool(false) }
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}
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val ognt_block = ognt.hasMultibeatData()
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val gnt_data_buffer = Reg(Vec(factor, UInt(width = outerDataBits)))
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val gnt_client_id = Reg(ognt.client_xact_id)
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val gnt_manager_id = Reg(ognt.manager_xact_id)
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val ignt_ctr = Counter(innerDataBeats)
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val ognt_ctr = Counter(factor)
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val sending_get = Reg(init = Bool(false))
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val get_block_grant = Grant(
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is_builtin_type = Bool(true),
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g_type = Grant.getDataBlockType,
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client_xact_id = gnt_client_id,
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manager_xact_id = gnt_manager_id,
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addr_beat = ignt_ctr.value,
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data = gnt_data_buffer.toBits)(innerConfig)
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val smallget_grant = ognt.g_type === Grant.getDataBeatType
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val get_grant = Grant(
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is_builtin_type = Bool(true),
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g_type = Grant.getDataBeatType,
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client_xact_id = ognt.client_xact_id,
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manager_xact_id = ognt.manager_xact_id,
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addr_beat = ognt.addr_beat >> UInt(log2Up(factor)),
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data = Fill(factor, ognt.data))(innerConfig)
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io.in.grant.valid := sending_get || (io.out.grant.valid && !ognt_block)
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io.out.grant.ready := !sending_get && (ognt_block || io.in.grant.ready)
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io.in.grant.bits := MuxBundle(Wire(io.in.grant.bits, init=ognt), Seq(
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sending_get -> get_block_grant,
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smallget_grant -> get_grant))
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when (io.out.grant.valid && ognt_block && !sending_get) {
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gnt_data_buffer(ognt_ctr.value) := ognt.data
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when (ognt_ctr.inc()) {
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gnt_client_id := ognt.client_xact_id
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gnt_manager_id := ognt.manager_xact_id
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sending_get := Bool(true)
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}
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}
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val data_chunks = Vec.tabulate(factor) { i =>
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val lsb = i * outerDataBits
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val msb = (i + 1) * outerDataBits - 1
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iacq.data(msb, lsb)
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}
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val beat_sel = Cat(mask_chunks.map(mask => mask.orR).reverse)
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val smallput_data = Mux1H(beat_sel, data_chunks)
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val smallput_wmask = Mux1H(beat_sel, mask_chunks)
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val smallput_beat = Cat(iacq.addr_beat, PriorityEncoder(beat_sel))
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assert(!io.in.acquire.valid || !smallput || PopCount(beat_sel) <= UInt(1),
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"Can't perform Put wider than outer width")
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val read_size_ok = MuxLookup(iacq.op_size(), Bool(false), Seq(
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MT_B -> Bool(true),
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MT_BU -> Bool(true),
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MT_H -> Bool(outerDataBits >= 16),
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MT_HU -> Bool(outerDataBits >= 16),
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MT_W -> Bool(outerDataBits >= 32),
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MT_WU -> Bool(outerDataBits >= 32),
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MT_D -> Bool(outerDataBits >= 64),
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MT_Q -> Bool(false)))
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assert(!io.in.acquire.valid || !smallget || read_size_ok,
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"Can't perform Get wider than outer width")
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val outerConfig = p.alterPartial({ case TLId => outerTLId })
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val innerConfig = p.alterPartial({ case TLId => innerTLId })
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val get_block_acquire = GetBlock(
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client_xact_id = iacq.client_xact_id,
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addr_block = iacq.addr_block,
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alloc = iacq.allocate())(outerConfig)
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val put_block_acquire = PutBlock(
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client_xact_id = acq_client_id,
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addr_block = acq_addr_block,
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addr_beat = if (factor > 1)
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Cat(acq_addr_beat, oacq_ctr.value)
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else acq_addr_beat,
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data = acq_data_buffer(outerDataBits - 1, 0),
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wmask = acq_wmask_buffer(outerWriteMaskBits - 1, 0))(outerConfig)
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val get_acquire = Get(
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client_xact_id = iacq.client_xact_id,
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addr_block = iacq.addr_block,
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addr_beat = outer_beat_addr,
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addr_byte = outer_byte_addr,
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operand_size = iacq.op_size(),
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alloc = iacq.allocate())(outerConfig)
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val put_acquire = Put(
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client_xact_id = iacq.client_xact_id,
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addr_block = iacq.addr_block,
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addr_beat = smallput_beat,
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data = smallput_data,
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wmask = Some(smallput_wmask))(outerConfig)
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val sending_put = Reg(init = Bool(false))
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val pass_valid = io.in.acquire.valid && !stretch
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io.out.acquire.bits := MuxBundle(Wire(io.out.acquire.bits, init=iacq), Seq(
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(sending_put, put_block_acquire),
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(shrink, get_block_acquire),
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(smallput, put_acquire),
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(smallget, get_acquire)))
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io.out.acquire.valid := sending_put || pass_valid
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io.in.acquire.ready := !sending_put && (stretch || io.out.acquire.ready)
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when (io.in.acquire.fire() && stretch) {
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acq_data_buffer := iacq.data
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acq_wmask_buffer := iacq.wmask()
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acq_client_id := iacq.client_xact_id
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acq_addr_block := iacq.addr_block
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acq_addr_beat := iacq.addr_beat
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sending_put := Bool(true)
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}
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when (sending_put && io.out.acquire.ready) {
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acq_data_buffer := acq_data_buffer >> outerDataBits
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acq_wmask_buffer := acq_wmask_buffer >> outerWriteMaskBits
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when (oacq_ctr.inc()) { sending_put := Bool(false) }
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}
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val ognt_block = ognt.hasMultibeatData()
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val gnt_data_buffer = Reg(Vec(factor, UInt(width = outerDataBits)))
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val gnt_client_id = Reg(ognt.client_xact_id)
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val gnt_manager_id = Reg(ognt.manager_xact_id)
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val ignt_ctr = Counter(innerDataBeats)
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val ognt_ctr = Counter(factor)
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val sending_get = Reg(init = Bool(false))
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val get_block_grant = Grant(
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is_builtin_type = Bool(true),
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g_type = Grant.getDataBlockType,
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client_xact_id = gnt_client_id,
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manager_xact_id = gnt_manager_id,
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addr_beat = ignt_ctr.value,
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data = gnt_data_buffer.toBits)(innerConfig)
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val smallget_grant = ognt.g_type === Grant.getDataBeatType
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val get_grant = Grant(
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is_builtin_type = Bool(true),
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g_type = Grant.getDataBeatType,
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client_xact_id = ognt.client_xact_id,
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manager_xact_id = ognt.manager_xact_id,
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addr_beat = ognt.addr_beat >> UInt(log2Up(factor)),
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data = Fill(factor, ognt.data))(innerConfig)
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io.in.grant.valid := sending_get || (io.out.grant.valid && !ognt_block)
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io.out.grant.ready := !sending_get && (ognt_block || io.in.grant.ready)
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io.in.grant.bits := MuxBundle(Wire(io.in.grant.bits, init=ognt), Seq(
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sending_get -> get_block_grant,
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smallget_grant -> get_grant))
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when (io.out.grant.valid && ognt_block && !sending_get) {
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gnt_data_buffer(ognt_ctr.value) := ognt.data
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when (ognt_ctr.inc()) {
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gnt_client_id := ognt.client_xact_id
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gnt_manager_id := ognt.manager_xact_id
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sending_get := Bool(true)
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}
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}
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when (io.in.grant.ready && sending_get) {
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ignt_ctr.inc()
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sending_get := Bool(false)
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}
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} else { io.out <> io.in }
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when (io.in.grant.ready && sending_get) {
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ignt_ctr.inc()
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sending_get := Bool(false)
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}
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}
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class MMIOTileLinkManagerData(implicit p: Parameters)
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