riscv/rocket-chip
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fix ignt_q logic

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This commit is contained in:
Howard Mao
2016-06-14 16:07:02 -07:00
parent 16bfbda3c9
commit 2789e60b6b
1 changed files with 1 additions and 1 deletions
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2
uncore/src/main/scala/trackers.scala
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@@ -385,7 +385,7 @@ trait AcceptsInnerAcquires extends HasAcquireMetadataBuffer
def innerAcquire(can_alloc: Bool, next: UInt) {
// Enqueue some metadata information that we'll use to make coherence updates with later
ignt_q.io.enq.valid := iacq_is_allocating || (iacq_is_merging && !iacq_same_xact)
ignt_q.io.enq.valid := iacq_is_allocating || (iacq_is_merging && io.iacq().first())
ignt_q.io.enq.bits := io.iacq()
// Use the outputs of the queue to make further messages