fix groundtests to fit new way of parameterizing TileLink clients
This commit is contained in:
parent
a921458758
commit
fe8d81958f
@ -16,15 +16,13 @@ class CacheFillTest(implicit p: Parameters) extends GroundTest()(p)
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val xact_pending = Reg(init = UInt(0, tlMaxClientXacts))
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val xact_id = PriorityEncoder(~xact_pending)
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disablePorts(mem = false)
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val (req_block, round_done) = Counter(io.mem.head.acquire.fire(), nblocks)
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val (req_block, round_done) = Counter(io.mem.acquire.fire(), nblocks)
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io.mem.acquire.valid := active && !xact_pending.andR
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io.mem.acquire.bits := Mux(state === s_prefetch,
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io.mem.head.acquire.valid := active && !xact_pending.andR
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io.mem.head.acquire.bits := Mux(state === s_prefetch,
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GetPrefetch(xact_id, UInt(memStartBlock) + req_block),
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GetBlock(xact_id, UInt(memStartBlock) + req_block))
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io.mem.grant.ready := xact_pending.orR
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io.mem.head.grant.ready := xact_pending.orR
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def add_pending(acq: DecoupledIO[Acquire]): UInt =
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Mux(acq.fire(), UIntToOH(acq.bits.client_xact_id), UInt(0))
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@ -36,8 +34,8 @@ class CacheFillTest(implicit p: Parameters) extends GroundTest()(p)
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}
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xact_pending := (xact_pending |
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add_pending(io.mem.acquire)) &
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remove_pending(io.mem.grant)
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add_pending(io.mem.head.acquire)) &
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remove_pending(io.mem.head.grant)
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when (state === s_start) { state := s_prefetch }
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when (state === s_prefetch && round_done) { state := s_retrieve }
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@ -51,8 +51,6 @@ class DmaStatusReg(implicit val p: Parameters) extends Module
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class DmaStreamTest(implicit p: Parameters) extends GroundTest()(p)
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with HasDmaParameters with HasCoreParameters with HasAddrMapParameters {
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disablePorts(cache = false, mem = false, ptw = false)
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val (s_start :: s_setup_req :: s_setup_wait ::
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s_stream_out :: s_stream_in :: s_stream_wait ::
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s_check_req :: s_check_wait :: s_done :: Nil) = Enum(Bits(), 9)
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@ -62,8 +60,8 @@ class DmaStreamTest(implicit p: Parameters) extends GroundTest()(p)
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val test_data = Vec.tabulate(conf.len) { i => UInt(i * 8, conf.size * 8) }
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val (req_index, req_done) = Counter(io.cache.req.fire(), conf.len)
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val (resp_index, resp_done) = Counter(io.cache.resp.fire(), conf.len)
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val (req_index, req_done) = Counter(io.cache.head.req.fire(), conf.len)
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val (resp_index, resp_done) = Counter(io.cache.head.resp.fire(), conf.len)
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val out_req = ClientDmaRequest(
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cmd = DMA_CMD_SOUT,
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@ -83,20 +81,21 @@ class DmaStreamTest(implicit p: Parameters) extends GroundTest()(p)
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frontend.io.cpu.req.valid := (state === s_stream_out) || (state === s_stream_in)
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frontend.io.cpu.req.bits := Mux(state === s_stream_out, out_req, in_req)
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io.ptw <> frontend.io.ptw
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io.mem <> frontend.io.mem
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io.ptw.head <> frontend.io.ptw
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io.mem.head <> frontend.io.mem
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val status_reg = Module(new DmaStatusReg)
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//status_reg.io.csr <> io.csr
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status_reg.io.incr_outstanding := frontend.io.incr_outstanding
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val cache_addr_base = Mux(state === s_setup_req, UInt(conf.source), UInt(conf.dest))
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val cache_req = io.cache.head.req
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io.cache.req.valid := (state === s_setup_req) || (state === s_check_req)
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io.cache.req.bits.addr := cache_addr_base + Cat(req_index, UInt(0, log2Up(conf.size)))
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io.cache.req.bits.data := test_data(req_index)
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io.cache.req.bits.typ := UInt(log2Up(conf.size))
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io.cache.req.bits.cmd := Mux(state === s_setup_req, M_XWR, M_XRD)
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cache_req.valid := (state === s_setup_req) || (state === s_check_req)
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cache_req.bits.addr := cache_addr_base + Cat(req_index, UInt(0, log2Up(conf.size)))
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cache_req.bits.data := test_data(req_index)
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cache_req.bits.typ := UInt(log2Up(conf.size))
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cache_req.bits.cmd := Mux(state === s_setup_req, M_XWR, M_XRD)
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when (state === s_start) { state := s_setup_req }
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when (state === s_setup_req && req_done) { state := s_setup_wait }
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@ -113,8 +112,8 @@ class DmaStreamTest(implicit p: Parameters) extends GroundTest()(p)
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when (dma_done) { state := s_check_req }
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val resp_data = io.cache.resp.bits.data(conf.size * 8 - 1, 0)
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assert(!io.cache.resp.valid || !io.cache.resp.bits.has_data ||
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val resp_data = io.cache.head.resp.bits.data(conf.size * 8 - 1, 0)
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assert(!io.cache.head.resp.valid || !io.cache.head.resp.bits.has_data ||
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resp_data === test_data(resp_index),
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"Result data streamed in does not match data streamed out")
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assert(!frontend.io.cpu.resp.valid || frontend.io.cpu.resp.bits.status === UInt(0),
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@ -133,8 +132,6 @@ class DmaTest(implicit p: Parameters) extends GroundTest()(p)
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private val wordBytes = wordBits / 8
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private val pAddrBits = p(PAddrBits)
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disablePorts(cache = false, mem = false, ptw = false)
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val sourceAddrs = Vec(testSet.map(test => UInt(test.source)))
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val destAddrs = Vec(testSet.map(test => UInt(test.dest)))
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val transferLengths = Vec(testSet.map(test => UInt(test.length)))
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@ -157,8 +154,8 @@ class DmaTest(implicit p: Parameters) extends GroundTest()(p)
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dst_start = destAddrs(testIdx),
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segment_size = transferLengths(testIdx))
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io.ptw <> frontend.io.ptw
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io.mem <> frontend.io.mem
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io.ptw.head <> frontend.io.ptw
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io.mem.head <> frontend.io.mem
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val status_reg = Module(new DmaStatusReg)
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//status_reg.io.csr <> io.csr
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@ -166,11 +163,13 @@ class DmaTest(implicit p: Parameters) extends GroundTest()(p)
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val dma_done = !frontend.io.busy && !status_reg.io.xact_outstanding
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io.cache.req.valid := (state === s_fill_req) || (state === s_check_req)
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io.cache.req.bits.addr := req_addr
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io.cache.req.bits.data := req_data
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io.cache.req.bits.typ := MT_W
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io.cache.req.bits.cmd := Mux(state === s_fill_req, M_XWR, M_XRD)
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val cache_resp = io.cache.head.resp
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val cache_req = io.cache.head.req
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cache_req.valid := (state === s_fill_req) || (state === s_check_req)
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cache_req.bits.addr := req_addr
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cache_req.bits.data := req_data
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cache_req.bits.typ := MT_W
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cache_req.bits.cmd := Mux(state === s_fill_req, M_XWR, M_XRD)
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when (state === s_start) {
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req_addr := sourceAddrs(testIdx)
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@ -179,13 +178,13 @@ class DmaTest(implicit p: Parameters) extends GroundTest()(p)
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state := s_fill_req
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}
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when (io.cache.req.fire()) {
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when (cache_req.fire()) {
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req_addr := req_addr + UInt(wordBytes)
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bytes_left := bytes_left - UInt(wordBytes)
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state := Mux(state === s_fill_req, s_fill_resp, s_check_resp)
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}
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when (state === s_fill_resp && io.cache.resp.valid) {
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when (state === s_fill_resp && cache_resp.valid) {
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req_data := req_data + UInt(dataStride)
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state := Mux(bytes_left === UInt(0), s_copy_req, s_fill_req)
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}
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@ -199,7 +198,7 @@ class DmaTest(implicit p: Parameters) extends GroundTest()(p)
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state := s_check_req
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}
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when (state === s_check_resp && io.cache.resp.valid) {
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when (state === s_check_resp && cache_resp.valid) {
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req_data := req_data + UInt(dataStride)
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when (bytes_left > UInt(0)) {
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state := s_check_req
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@ -219,11 +218,11 @@ class DmaTest(implicit p: Parameters) extends GroundTest()(p)
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require(length % wordBytes == 0, "transfer length must be word-aligned")
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}
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assert(!io.cache.resp.valid || !io.cache.resp.bits.has_data ||
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io.cache.resp.bits.data === req_data, "Received data does not match")
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assert(!cache_resp.valid || !cache_resp.bits.has_data ||
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cache_resp.bits.data === req_data, "Received data does not match")
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assert(!frontend.io.cpu.resp.valid || frontend.io.cpu.resp.bits.status === UInt(0),
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"Frontend error response")
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val cache_timeout = Timer(1000, io.cache.req.fire(), io.cache.resp.valid)
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val cache_timeout = Timer(1000, cache_req.fire(), cache_resp.valid)
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assert(!cache_timeout, "Memory request timed out")
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}
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@ -7,17 +7,12 @@ import rocket._
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import scala.util.Random
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import cde.{Parameters, Field}
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case object NGenerators extends Field[Int]
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case object GenerateUncached extends Field[Boolean]
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case object GenerateCached extends Field[Boolean]
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case object MaxGenerateRequests extends Field[Int]
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case object GeneratorStartAddress extends Field[BigInt]
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trait HasGeneratorParams {
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trait HasGeneratorParameters extends HasGroundTestParameters {
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implicit val p: Parameters
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val nGens = p(NGenerators)
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val genUncached = p(GenerateUncached)
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val genCached = p(GenerateCached)
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val nGens = p(NTiles) * (nUncached + nCached)
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val genTimeout = 4096
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val maxRequests = p(MaxGenerateRequests)
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val startAddress = p(GeneratorStartAddress)
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@ -30,7 +25,7 @@ trait HasGeneratorParams {
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}
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class UncachedTileLinkGenerator(id: Int)
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(implicit p: Parameters) extends TLModule()(p) with HasGeneratorParams {
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(implicit p: Parameters) extends TLModule()(p) with HasGeneratorParameters {
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private val tlBlockOffset = tlBeatAddrBits + tlByteAddrBits
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@ -61,22 +56,13 @@ class UncachedTileLinkGenerator(id: Int)
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io.finished := (state === s_finished)
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val part_of_full_addr =
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if (genCached) {
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Cat(req_cnt,
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UInt(0, width = 1),
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UInt(0, wordOffset))
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} else {
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Cat(req_cnt,
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UInt(0, wordOffset))
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}
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val another_part_of_full_addr =
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if (log2Ceil(nGens) > 0) {
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Cat(UInt(id, log2Ceil(nGens)),
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part_of_full_addr)
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UInt(0, wordOffset))
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} else {
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part_of_full_addr
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UInt(0, wordOffset)
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}
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val full_addr = UInt(startAddress) + another_part_of_full_addr
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val full_addr = UInt(startAddress) + Cat(req_cnt, part_of_full_addr)
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val addr_block = full_addr >> UInt(tlBlockOffset)
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val addr_beat = full_addr(tlBlockOffset - 1, tlByteAddrBits)
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@ -124,7 +110,7 @@ class UncachedTileLinkGenerator(id: Int)
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}
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class HellaCacheGenerator(id: Int)
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(implicit p: Parameters) extends L1HellaCacheModule()(p) with HasGeneratorParams {
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(implicit p: Parameters) extends L1HellaCacheModule()(p) with HasGeneratorParameters {
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val io = new Bundle {
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val finished = Bool(OUTPUT)
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val mem = new HellaCacheIO
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@ -140,23 +126,12 @@ class HellaCacheGenerator(id: Int)
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val (req_cnt, req_wrap) = Counter(io.mem.resp.valid, maxRequests)
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val part_of_req_addr =
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if (log2Ceil(nGens) > 0) {
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if (genUncached) {
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Cat(UInt(id, log2Ceil(nGens)),
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UInt(1, width = 1),
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UInt(0, wordOffset))
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} else {
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Cat(UInt(id, log2Ceil(nGens)),
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UInt(0, wordOffset))
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}
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} else {
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if (genUncached) {
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Cat(UInt(1, width = 1),
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UInt(0, wordOffset))
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} else {
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UInt(0, wordOffset)
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}
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}
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if (log2Ceil(nGens) > 0) {
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Cat(UInt(id, log2Ceil(nGens)),
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UInt(0, wordOffset))
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} else {
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UInt(0, wordOffset)
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}
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val req_addr = UInt(startAddress) + Cat(req_cnt, part_of_req_addr)
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val req_data = Cat(UInt(id, log2Up(nGens)), req_addr)
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@ -191,23 +166,23 @@ class HellaCacheGenerator(id: Int)
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}
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class GeneratorTest(id: Int)(implicit p: Parameters)
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extends GroundTest()(p) with HasGeneratorParams {
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extends GroundTest()(p) with HasGeneratorParameters {
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disablePorts(mem = !genUncached, cache = !genCached)
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val totalGens = nUncached + nCached
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val gen_finished = Wire(init = Vec.fill(2){Bool(true)})
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if (genUncached) {
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val uncacheGen = Module(new UncachedTileLinkGenerator(id))
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io.mem <> uncacheGen.io.mem
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gen_finished(0) := uncacheGen.io.finished
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val cached = List.tabulate(nCached) { i =>
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val realId = id * totalGens + i
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Module(new HellaCacheGenerator(realId))
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}
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if (genCached) {
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val cacheGen = Module(new HellaCacheGenerator(id))
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io.cache <> cacheGen.io.mem
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gen_finished(1) := cacheGen.io.finished
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val uncached = List.tabulate(nUncached) { i =>
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val realId = id * totalGens + nCached + i
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Module(new UncachedTileLinkGenerator(realId))
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}
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io.cache <> cached.map(_.io.mem)
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io.mem <> uncached.map(_.io.mem)
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val gen_finished = cached.map(_.io.finished) ++ uncached.map(_.io.finished)
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io.finished := gen_finished.reduce(_ && _)
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}
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@ -151,8 +151,6 @@ class NastiSequencer(n: Int)(implicit p: Parameters) extends Module {
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class NastiConverterTest(implicit p: Parameters) extends GroundTest()(p)
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with HasNastiParameters {
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disablePorts(mem = false)
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val tests = Seq(Module(new NastiBlockTest), Module(new NastiSmallTest))
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val sequencer = Module(new NastiSequencer(tests.size))
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@ -162,7 +160,7 @@ class NastiConverterTest(implicit p: Parameters) extends GroundTest()(p)
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sequencer.io.in <> tests.map(_.io.mem)
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sequencer.io.finished := tests.map(_.io.finished)
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converter.io.nasti <> sequencer.io.out
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TileLinkWidthAdapter(converter.io.tl, io.mem)
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TileLinkWidthAdapter(converter.io.tl, io.mem.head)
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io.finished := tests.map(_.io.finished).reduce(_ && _)
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}
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@ -494,8 +494,6 @@ object RegressionTests {
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case object GroundTestRegressions extends Field[Parameters => Seq[Regression]]
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class RegressionTest(implicit p: Parameters) extends GroundTest()(p) {
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disablePorts(mem = false, cache = false)
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val regressions = p(GroundTestRegressions)(p)
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val regressIOs = Vec(regressions.map(_.io))
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val regress_idx = Reg(init = UInt(0, log2Up(regressions.size + 1)))
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@ -507,12 +505,12 @@ class RegressionTest(implicit p: Parameters) extends GroundTest()(p) {
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regressIOs.zipWithIndex.foreach { case (regress, i) =>
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val me = regress_idx === UInt(i)
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regress.start := me && start
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regress.mem.acquire.ready := io.mem.acquire.ready && me
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regress.mem.grant.valid := io.mem.grant.valid && me
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regress.mem.grant.bits := io.mem.grant.bits
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regress.cache.req.ready := io.cache.req.ready && me
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regress.cache.resp.valid := io.cache.resp.valid && me
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regress.cache.resp.bits := io.cache.resp.bits
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regress.mem.acquire.ready := io.mem.head.acquire.ready && me
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regress.mem.grant.valid := io.mem.head.grant.valid && me
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regress.mem.grant.bits := io.mem.head.grant.bits
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regress.cache.req.ready := io.cache.head.req.ready && me
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regress.cache.resp.valid := io.cache.head.resp.valid && me
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regress.cache.resp.bits := io.cache.head.resp.bits
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}
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val cur_regression = regressIOs(regress_idx)
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@ -520,12 +518,12 @@ class RegressionTest(implicit p: Parameters) extends GroundTest()(p) {
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val cur_grant = cur_regression.mem.grant
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val cur_cache = cur_regression.cache
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io.mem.acquire.valid := cur_acquire.valid
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io.mem.acquire.bits := cur_acquire.bits
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io.mem.grant.ready := cur_grant.ready
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io.cache.req.valid := cur_cache.req.valid
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io.cache.req.bits := cur_cache.req.bits
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io.cache.invalidate_lr := cur_cache.invalidate_lr
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io.mem.head.acquire.valid := cur_acquire.valid
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io.mem.head.acquire.bits := cur_acquire.bits
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io.mem.head.grant.ready := cur_grant.ready
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io.cache.head.req.valid := cur_cache.req.valid
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io.cache.head.req.bits := cur_cache.req.bits
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io.cache.head.invalidate_lr := cur_cache.invalidate_lr
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when (cur_regression.finished && !all_done) {
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start := Bool(true)
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@ -537,5 +535,6 @@ class RegressionTest(implicit p: Parameters) extends GroundTest()(p) {
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val timeout = Timer(5000, start, cur_regression.finished)
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assert(!timeout, "Regression timed out")
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assert(!(all_done && io.mem.grant.valid), "Getting grant after test completion")
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assert(!(all_done && io.mem.head.grant.valid),
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"Getting grant after test completion")
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}
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@ -5,6 +5,7 @@ import rocket._
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import uncore._
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import junctions._
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import scala.util.Random
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import scala.collection.mutable.ListBuffer
|
||||
import cde.{Parameters, Field}
|
||||
|
||||
case object BuildGroundTest extends Field[(Int, Parameters) => GroundTest]
|
||||
@ -12,6 +13,19 @@ case object GroundTestMaxXacts extends Field[Int]
|
||||
case object GroundTestCSRs extends Field[Seq[Int]]
|
||||
case object TohostAddr extends Field[BigInt]
|
||||
|
||||
case object GroundTestCachedClients extends Field[Int]
|
||||
case object GroundTestUncachedClients extends Field[Int]
|
||||
case object GroundTestNPTW extends Field[Int]
|
||||
|
||||
trait HasGroundTestParameters extends HasAddrMapParameters {
|
||||
implicit val p: Parameters
|
||||
val nUncached = p(GroundTestUncachedClients)
|
||||
val nCached = p(GroundTestCachedClients)
|
||||
val nPTW = p(GroundTestNPTW)
|
||||
val memStart = addrMap("mem").start
|
||||
val memStartBlock = memStart >> p(CacheBlockOffsetBits)
|
||||
}
|
||||
|
||||
/** A "cache" that responds to probe requests with a release indicating
|
||||
* the block is not present */
|
||||
class DummyCache(implicit val p: Parameters) extends Module {
|
||||
@ -27,6 +41,7 @@ class DummyCache(implicit val p: Parameters) extends Module {
|
||||
io.grant.ready := Bool(true)
|
||||
io.release.valid := (state === s_release)
|
||||
io.release.bits := coh.makeRelease(req)
|
||||
io.finish.valid := Bool(false)
|
||||
|
||||
when (io.probe.fire()) {
|
||||
req := io.probe.bits
|
||||
@ -76,34 +91,17 @@ class DummyPTW(n: Int)(implicit p: Parameters) extends CoreModule()(p) {
|
||||
}
|
||||
}
|
||||
|
||||
class GroundTestIO(implicit p: Parameters) extends ParameterizedBundle()(p) {
|
||||
val cache = new HellaCacheIO
|
||||
val mem = new ClientUncachedTileLinkIO
|
||||
val dma = new DmaIO
|
||||
val ptw = new TLBPTWIO
|
||||
class GroundTestIO(implicit val p: Parameters) extends ParameterizedBundle()(p)
|
||||
with HasGroundTestParameters {
|
||||
val cache = Vec(nCached, new HellaCacheIO)
|
||||
val mem = Vec(nUncached, new ClientUncachedTileLinkIO)
|
||||
val ptw = Vec(nPTW, new TLBPTWIO)
|
||||
val finished = Bool(OUTPUT)
|
||||
}
|
||||
|
||||
abstract class GroundTest(implicit val p: Parameters) extends Module
|
||||
with HasAddrMapParameters {
|
||||
with HasGroundTestParameters {
|
||||
val io = new GroundTestIO
|
||||
val memStart = addrMap("mem").start
|
||||
val memStartBlock = memStart >> p(CacheBlockOffsetBits)
|
||||
|
||||
def disablePorts(mem: Boolean = true,
|
||||
cache: Boolean = true,
|
||||
ptw: Boolean = true) {
|
||||
if (mem) {
|
||||
io.mem.acquire.valid := Bool(false)
|
||||
io.mem.grant.ready := Bool(false)
|
||||
}
|
||||
if (cache) {
|
||||
io.cache.req.valid := Bool(false)
|
||||
}
|
||||
if (ptw) {
|
||||
io.ptw.req.valid := Bool(false)
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
class GroundTestFinisher(implicit p: Parameters) extends TLModule()(p) {
|
||||
@ -134,31 +132,51 @@ class GroundTestFinisher(implicit p: Parameters) extends TLModule()(p) {
|
||||
}
|
||||
|
||||
class GroundTestTile(id: Int, resetSignal: Bool)
|
||||
(implicit val p: Parameters) extends Tile(resetSignal = resetSignal)(p) {
|
||||
(implicit val p: Parameters)
|
||||
extends Tile(resetSignal = resetSignal)(p)
|
||||
with HasGroundTestParameters {
|
||||
|
||||
val test = p(BuildGroundTest)(id, dcacheParams)
|
||||
|
||||
val dcache = Module(new HellaCache()(dcacheParams))
|
||||
val dcacheIF = Module(new SimpleHellaCacheIF()(dcacheParams))
|
||||
dcacheIF.io.requestor <> test.io.cache
|
||||
dcache.io.cpu <> dcacheIF.io.cache
|
||||
io.cached.head <> dcache.io.mem
|
||||
val ptwPorts = ListBuffer.empty ++= test.io.ptw
|
||||
val memPorts = ListBuffer.empty ++= test.io.mem
|
||||
|
||||
// SimpleHellaCacheIF leaves invalidate_lr dangling, so we wire it to false
|
||||
dcache.io.cpu.invalidate_lr := Bool(false)
|
||||
if (nCached > 0) {
|
||||
val dcache = Module(new HellaCache()(dcacheParams))
|
||||
val dcacheArb = Module(new HellaCacheArbiter(nCached)(dcacheParams))
|
||||
|
||||
val ptw = Module(new DummyPTW(2))
|
||||
ptw.io.requestors(0) <> test.io.ptw
|
||||
ptw.io.requestors(1) <> dcache.io.ptw
|
||||
dcacheArb.io.requestor.zip(test.io.cache).foreach {
|
||||
case (requestor, cache) =>
|
||||
val dcacheIF = Module(new SimpleHellaCacheIF()(dcacheParams))
|
||||
dcacheIF.io.requestor <> cache
|
||||
requestor <> dcacheIF.io.cache
|
||||
}
|
||||
dcache.io.cpu <> dcacheArb.io.mem
|
||||
io.cached.head <> dcache.io.mem
|
||||
|
||||
// SimpleHellaCacheIF leaves invalidate_lr dangling, so we wire it to false
|
||||
dcache.io.cpu.invalidate_lr := Bool(false)
|
||||
|
||||
ptwPorts += dcache.io.ptw
|
||||
} else {
|
||||
val dcache = Module(new DummyCache)
|
||||
io.cached.head <> dcache.io
|
||||
}
|
||||
|
||||
// Only Tile 0 needs to write tohost
|
||||
if (id == 0) {
|
||||
val finisher = Module(new GroundTestFinisher)
|
||||
finisher.io.finished := test.io.finished
|
||||
memPorts += finisher.io.mem
|
||||
}
|
||||
|
||||
val memArb = Module(new ClientUncachedTileLinkIOArbiter(2))
|
||||
memArb.io.in(0) <> test.io.mem
|
||||
memArb.io.in(1) <> finisher.io.mem
|
||||
io.uncached.head <> memArb.io.out
|
||||
} else { io.uncached.head <> test.io.mem }
|
||||
if (ptwPorts.size > 0) {
|
||||
val ptw = Module(new DummyPTW(ptwPorts.size))
|
||||
ptw.io.requestors <> ptwPorts
|
||||
}
|
||||
|
||||
require(memPorts.size == io.uncached.size)
|
||||
if (memPorts.size > 0) {
|
||||
io.uncached <> memPorts
|
||||
}
|
||||
}
|
||||
|
@ -57,7 +57,7 @@ case object AddressBag extends Field[List[Int]]
|
||||
|
||||
trait HasTraceGenParams {
|
||||
implicit val p: Parameters
|
||||
val numGens = p(NGenerators)
|
||||
val numGens = p(NTiles)
|
||||
val numBitsInId = log2Up(numGens)
|
||||
val numReqsPerGen = p(MaxGenerateRequests)
|
||||
val memRespTimeout = 1024
|
||||
@ -547,10 +547,8 @@ class TraceGenerator(id: Int)
|
||||
class GroundTestTraceGenerator(id: Int)(implicit p: Parameters)
|
||||
extends GroundTest()(p) with HasTraceGenParams {
|
||||
|
||||
disablePorts(cache = false)
|
||||
|
||||
val traceGen = Module(new TraceGenerator(id))
|
||||
io.cache <> traceGen.io.mem
|
||||
io.cache.head <> traceGen.io.mem
|
||||
|
||||
io.finished := traceGen.io.finished
|
||||
}
|
||||
|
@ -593,8 +593,6 @@ class AtosConverterTest(implicit p: Parameters) extends UnitTest {
|
||||
}
|
||||
|
||||
class UnitTestSuite(implicit p: Parameters) extends GroundTest()(p) {
|
||||
disablePorts()
|
||||
|
||||
val tests = Seq(
|
||||
Module(new MultiWidthFifoTest),
|
||||
Module(new NastiIOHostIOConverterTest),
|
||||
|
Loading…
Reference in New Issue
Block a user