riscv/rocket-chip
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make sure clocks and reset signals get intialized properly

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This commit is contained in:
Howard Mao 2016-06-08 10:03:53 -07:00
parent 99b257316e
commit a809a1712a
2 changed files with 2 additions and 2 deletions
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2
junctions

@ -1 +1 @@
Subproject commit 4562d3c98eb677f2aea47692e02006efcf260800
Subproject commit 546aaad8cfb03e45e068733c2b694232bcf9dcdb

2
vsrc/rocketTestHarness.v
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@ -62,7 +62,7 @@ module rocketTestHarness;
reg clk = 1'b0;
reg reset = 1'b1;
reg r_reset;
reg r_reset = 1'b1;
reg start = 1'b0;
always #`CLOCK_PERIOD clk = ~clk;