riscv/rocket-chip
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Merge sptbr and sasid

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This commit is contained in:
Andrew Waterman 2016-06-17 18:29:05 -07:00
parent 0b4c8e9af7
commit 60bddddfe6
8 changed files with 24 additions and 16 deletions
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16
rocket/src/main/scala/csr.scala
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@ -71,6 +71,12 @@ class MIP extends Bundle {
val usip = Bool()
}
class PTBR(implicit p: Parameters) extends CoreBundle()(p) {
require(maxPAddrBits - pgIdxBits + asIdBits <= xLen)
val asid = UInt(width = asIdBits)
val ppn = UInt(width = maxPAddrBits - pgIdxBits)
}
object PRV
{
val SZ = 2
@ -110,7 +116,7 @@ class CSRFileIO(implicit p: Parameters) extends CoreBundle {
val singleStep = Bool(OUTPUT)
val status = new MStatus().asOutput
val ptbr = UInt(OUTPUT, paddrBits)
val ptbr = new PTBR().asOutput
val evec = UInt(OUTPUT, vaddrBitsExtended)
val exception = Bool(INPUT)
val retire = UInt(INPUT, log2Up(1+retireWidth))
@ -197,7 +203,7 @@ class CSRFile(implicit p: Parameters) extends CoreModule()(p)
val reg_sbadaddr = Reg(UInt(width = vaddrBitsExtended))
val reg_sscratch = Reg(Bits(width = xLen))
val reg_stvec = Reg(UInt(width = vaddrBits))
val reg_sptbr = Reg(UInt(width = ppnBits))
val reg_sptbr = Reg(new PTBR)
val reg_wfi = Reg(init=Bool(false))
val reg_uarch_counters = io.uarch_counters.map(WideCounter(xLen, _))
@ -297,8 +303,7 @@ class CSRFile(implicit p: Parameters) extends CoreModule()(p)
read_mapping += CSRs.sscratch -> reg_sscratch
read_mapping += CSRs.scause -> reg_scause
read_mapping += CSRs.sbadaddr -> reg_sbadaddr.sextTo(xLen)
read_mapping += CSRs.sptbr -> reg_sptbr
read_mapping += CSRs.sasid -> UInt(0)
read_mapping += CSRs.sptbr -> reg_sptbr.toBits
read_mapping += CSRs.sepc -> reg_sepc.sextTo(xLen)
read_mapping += CSRs.stvec -> reg_stvec.sextTo(xLen)
read_mapping += CSRs.mscounteren -> UInt(0)
@ -522,7 +527,7 @@ class CSRFile(implicit p: Parameters) extends CoreModule()(p)
}
when (decoded_addr(CSRs.sie)) { reg_mie := (reg_mie & ~reg_mideleg) | (wdata & reg_mideleg) }
when (decoded_addr(CSRs.sscratch)) { reg_sscratch := wdata }
when (decoded_addr(CSRs.sptbr)) { reg_sptbr := wdata }
when (decoded_addr(CSRs.sptbr)) { reg_sptbr.ppn := wdata(ppnBits-1,0) }
when (decoded_addr(CSRs.sepc)) { reg_sepc := wdata >> log2Up(coreInstBytes) << log2Up(coreInstBytes) }
when (decoded_addr(CSRs.stvec)) { reg_stvec := wdata >> 2 << 2 }
when (decoded_addr(CSRs.scause)) { reg_scause := wdata & UInt((BigInt(1) << (xLen-1)) + 31) /* only implement 5 LSBs and MSB */ }
@ -559,6 +564,7 @@ class CSRFile(implicit p: Parameters) extends CoreModule()(p)
reg_mstatus.mprv := false
}
reg_sptbr.asid := 0
reg_tdrselect.reserved := 0
reg_tdrselect.tdrmode := true // TODO support D-mode breakpoint theft
if (reg_bp.isEmpty) reg_tdrselect.tdrindex := 0

1
rocket/src/main/scala/dcache.scala
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@ -104,7 +104,6 @@ class DCache(implicit p: Parameters) extends L1HellaCacheModule()(p) {
io.ptw <> tlb.io.ptw
tlb.io.req.valid := s1_valid_masked && s1_readwrite
tlb.io.req.bits.passthrough := s1_req.phys
tlb.io.req.bits.asid := 0
tlb.io.req.bits.vpn := s1_req.addr >> pgIdxBits
tlb.io.req.bits.instruction := false
tlb.io.req.bits.store := s1_write

1
rocket/src/main/scala/frontend.scala
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@ -96,7 +96,6 @@ class Frontend(implicit p: Parameters) extends CoreModule()(p) with HasL1CachePa
io.ptw <> tlb.io.ptw
tlb.io.req.valid := !stall && !icmiss
tlb.io.req.bits.vpn := s1_pc >> pgIdxBits
tlb.io.req.bits.asid := UInt(0)
tlb.io.req.bits.passthrough := Bool(false)
tlb.io.req.bits.instruction := Bool(true)
tlb.io.req.bits.store := Bool(false)

2
rocket/src/main/scala/instructions.scala
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@ -259,7 +259,6 @@ object CSRs {
val sbadaddr = 0x143
val sip = 0x144
val sptbr = 0x180
val sasid = 0x181
val scycle = 0xd00
val stime = 0xd01
val sinstret = 0xd02
@ -326,7 +325,6 @@ object CSRs {
res += sbadaddr
res += sip
res += sptbr
res += sasid
res += scycle
res += stime
res += sinstret

1
rocket/src/main/scala/nbdcache.scala
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@ -817,7 +817,6 @@ class HellaCache(implicit p: Parameters) extends L1HellaCacheModule()(p) {
io.ptw <> dtlb.io.ptw
dtlb.io.req.valid := s1_valid_masked && s1_readwrite
dtlb.io.req.bits.passthrough := s1_req.phys
dtlb.io.req.bits.asid := UInt(0)
dtlb.io.req.bits.vpn := s1_req.addr >> pgIdxBits
dtlb.io.req.bits.instruction := Bool(false)
dtlb.io.req.bits.store := s1_write

8
rocket/src/main/scala/ptw.scala
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@ -21,12 +21,13 @@ class PTWResp(implicit p: Parameters) extends CoreBundle()(p) {
class TLBPTWIO(implicit p: Parameters) extends CoreBundle()(p) {
val req = Decoupled(new PTWReq)
val resp = Valid(new PTWResp).flip
val status = new MStatus().asInput
val ptbr = new PTBR().asInput
val invalidate = Bool(INPUT)
val status = new MStatus().asInput
}
class DatapathPTWIO(implicit p: Parameters) extends CoreBundle()(p) {
val ptbr = UInt(INPUT, ppnBits)
val ptbr = new PTBR().asInput
val invalidate = Bool(INPUT)
val status = new MStatus().asInput
}
@ -78,7 +79,7 @@ class PTW(n: Int)(implicit p: Parameters) extends CoreModule()(p) {
when (arb.io.out.fire()) {
r_req := arb.io.out.bits
r_req_dest := arb.io.chosen
r_pte.ppn := io.dpath.ptbr
r_pte.ppn := io.dpath.ptbr.ppn
}
val (pte_cache_hit, pte_cache_data) = {
@ -130,6 +131,7 @@ class PTW(n: Int)(implicit p: Parameters) extends CoreModule()(p) {
io.requestor(i).resp.valid := resp_val && (r_req_dest === i)
io.requestor(i).resp.bits.pte := r_pte
io.requestor(i).resp.bits.pte.ppn := resp_ppn
io.requestor(i).ptbr := io.dpath.ptbr
io.requestor(i).invalidate := io.dpath.invalidate
io.requestor(i).status := io.dpath.status
}

8
rocket/src/main/scala/rocket.scala
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@ -66,7 +66,13 @@ trait HasCoreParameters extends HasAddrMapParameters {
val enableCommitLog = false
val usingPerfCounters = p(UsePerfCounters)
if (fastLoadByte) require(fastLoadWord)
val maxPAddrBits = xLen match {
case 32 => 34
case 64 => 50
}
require(paddrBits < maxPAddrBits)
require(!fastLoadByte || fastLoadWord)
}
abstract class CoreModule(implicit val p: Parameters) extends Module

3
rocket/src/main/scala/tlb.scala
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@ -56,7 +56,6 @@ class RocketCAM(implicit p: Parameters) extends TLBModule()(p) {
}
class TLBReq(implicit p: Parameters) extends CoreBundle()(p) {
val asid = UInt(width = asIdBits)
val vpn = UInt(width = vpnBitsExtended)
val passthrough = Bool()
val instruction = Bool()
@ -92,7 +91,7 @@ class TLB(implicit p: Parameters) extends TLBModule()(p) {
val r_refill_waddr = Reg(tag_cam.io.write_addr)
val r_req = Reg(new TLBReq)
val lookup_tag = Cat(io.req.bits.asid, io.req.bits.vpn(vpnBits-1,0)).toUInt
val lookup_tag = Cat(io.ptw.ptbr.asid, io.req.bits.vpn(vpnBits-1,0)).toUInt
tag_cam.io.tag := lookup_tag
tag_cam.io.write := state === s_wait && io.ptw.resp.valid
tag_cam.io.write_tag := r_refill_tag