make Memtest generators more configurable
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2163ebfca3
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@ -21,9 +21,10 @@ trait HasGeneratorParams {
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val genTimeout = 4096
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val maxRequests = p(MaxGenerateRequests)
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val startAddress = p(GeneratorStartAddress)
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val genWordBits = p(WordBits)
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val genWordBits = 32
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val genWordBytes = genWordBits / 8
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val wordOffset = log2Up(genWordBytes)
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val wordSize = MT_WU
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require(startAddress % BigInt(genWordBytes) == 0)
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}
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@ -101,7 +102,7 @@ class UncachedTileLinkGenerator(id: Int)
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addr_block = addr_block,
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addr_beat = addr_beat,
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addr_byte = addr_byte,
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operand_size = MT_D,
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operand_size = wordSize,
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alloc = Bool(false))
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io.mem.acquire.valid := sending && !io.finished
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@ -157,12 +158,12 @@ class HellaCacheGenerator(id: Int)
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}
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}
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val req_addr = UInt(startAddress) + Cat(req_cnt, part_of_req_addr)
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val req_data = Cat(UInt(id, log2Up(nGens)), req_cnt, req_addr)
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val req_data = Cat(UInt(id, log2Up(nGens)), req_addr)
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io.mem.req.valid := sending && !io.finished
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io.mem.req.bits.addr := req_addr
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io.mem.req.bits.data := req_data
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io.mem.req.bits.typ := MT_D
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io.mem.req.bits.typ := wordSize
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io.mem.req.bits.cmd := Mux(state === s_write, M_XWR, M_XRD)
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io.mem.req.bits.tag := UInt(0)
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@ -176,7 +177,7 @@ class HellaCacheGenerator(id: Int)
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io.finished := (state === s_finished)
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assert(!io.mem.resp.valid || !io.mem.resp.bits.has_data ||
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io.mem.resp.bits.data === req_data,
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io.mem.resp.bits.data(genWordBits - 1, 0) === req_data,
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s"Received incorrect data in cached generator ${id}")
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}
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