remove implicit modulo addressing in FPU (#44)
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@ -561,7 +561,7 @@ class FPU(implicit p: Parameters) extends CoreModule()(p) {
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}
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val waddr = Mux(divSqrt_wen, divSqrt_waddr, winfo(0)(4,0).toUInt)
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val wsrc = (winfo(0) >> 6)
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val wsrc = (winfo(0) >> 6)(log2Up(pipes.size) - 1,0)
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val wcp = winfo(0)(6+log2Up(pipes.size))
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val wdata = Mux(divSqrt_wen, divSqrt_wdata, Vec(pipes.map(_.res.data))(wsrc))
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val wexc = Vec(pipes.map(_.res.exc))(wsrc)
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