fully disable the cache when not using it in regression tests
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3e105eb352
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@ -18,6 +18,17 @@ abstract class Regression(implicit val p: Parameters)
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val memStart = addrMap("mem").start
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val memStartBlock = memStart >> p(CacheBlockOffsetBits)
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val io = new RegressionIO
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def disableCache() {
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io.cache.req.valid := Bool(false)
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io.cache.req.bits.addr := UInt(memStart)
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io.cache.req.bits.typ := MT_D
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io.cache.req.bits.cmd := M_XRD
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io.cache.req.bits.tag := UInt(0)
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io.cache.req.bits.data := Bits(0)
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io.cache.req.bits.phys := Bool(true)
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io.cache.invalidate_lr := Bool(false)
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}
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}
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/**
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@ -55,6 +66,7 @@ class IOGetAfterPutBlockRegression(implicit p: Parameters) extends Regression()(
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io.cache.req.bits.typ := MT_W
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io.cache.req.bits.cmd := M_XRD
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io.cache.req.bits.tag := UInt(0)
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io.cache.invalidate_lr := Bool(false)
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when (put_done) { put_sent := Bool(true) }
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when (io.cache.req.fire()) { get_sent := Bool(true) }
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@ -84,7 +96,7 @@ class PutBlockMergeRegression(implicit p: Parameters)
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val s_idle :: s_put :: s_wait :: s_done :: Nil = Enum(Bits(), 4)
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val state = Reg(init = s_idle)
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io.cache.req.valid := Bool(false)
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disableCache()
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val l2params = p.alterPartial({ case CacheName => "L2Bank" })
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val nSets = l2params(NSets)
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@ -163,7 +175,8 @@ class NoAllocPutHitRegression(implicit p: Parameters) extends Regression()(p) {
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"NoAllocPutHitRegression: data does not match")
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io.finished := (state === s_done)
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io.cache.req.valid := Bool(false)
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disableCache()
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}
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/** Make sure L2 does the right thing when multiple puts are sent for the
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@ -223,13 +236,15 @@ class MixedAllocPutRegression(implicit p: Parameters) extends Regression()(p) {
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assert(state =/= s_get_wait || !io.mem.grant.valid ||
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io.mem.grant.bits.data === get_data(io.mem.grant.bits.client_xact_id),
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"MixedAllocPutRegression: data mismatch")
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disableCache()
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}
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/* Make sure each no-alloc put triggers a request to outer memory.
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* Unfortunately, there's no way to verify that this works except by looking
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* at the waveform */
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class RepeatedNoAllocPutRegression(implicit p: Parameters) extends Regression()(p) {
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io.cache.req.valid := Bool(false)
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disableCache()
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val nPuts = 2
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val (put_beat, put_done) = Counter(io.mem.acquire.fire(), tlDataBeats)
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@ -260,7 +275,7 @@ class RepeatedNoAllocPutRegression(implicit p: Parameters) extends Regression()(
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/* Make sure write masking works properly by writing a block of data
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* piece by piece */
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class WriteMaskedPutBlockRegression(implicit p: Parameters) extends Regression()(p) {
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io.cache.req.valid := Bool(false)
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disableCache()
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val (s_idle :: s_put_send :: s_put_ack :: s_stall ::
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s_get_send :: s_get_ack :: s_done :: Nil) = Enum(Bits(), 7)
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@ -325,7 +340,7 @@ class WriteMaskedPutBlockRegression(implicit p: Parameters) extends Regression()
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/* Make sure a prefetch that hits returns immediately. */
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class PrefetchHitRegression(implicit p: Parameters) extends Regression()(p) {
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io.cache.req.valid := Bool(false)
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disableCache()
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val sending = Reg(init = Bool(false))
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val nPrefetches = 2
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@ -356,7 +371,7 @@ class PrefetchHitRegression(implicit p: Parameters) extends Regression()(p) {
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* Each request has the same client_xact_id, but there are multiple in flight.
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* The responses therefore must come back in the order they are sent. */
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class SequentialSameIdGetRegression(implicit p: Parameters) extends Regression()(p) {
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io.cache.req.valid := Bool(false)
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disableCache()
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val sending = Reg(init = Bool(false))
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val finished = Reg(init = Bool(false))
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@ -386,7 +401,7 @@ class SequentialSameIdGetRegression(implicit p: Parameters) extends Regression()
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* test multibank configurations, we'll have to think of some other way to
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* determine which banks are conflicting */
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class WritebackRegression(implicit p: Parameters) extends Regression()(p) {
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io.cache.req.valid := Bool(false)
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disableCache()
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val l2params = p.alterPartial({ case CacheName => "L2Bank" })
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val nSets = l2params(NSets)
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@ -442,7 +457,7 @@ class PutBeforePutBlockRegression(implicit p: Parameters) extends Regression()(p
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s_finished :: Nil) = Enum(Bits(), 5)
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val state = Reg(init = s_idle)
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io.cache.req.valid := Bool(false)
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disableCache()
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val (put_block_beat, put_block_done) = Counter(
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state === s_putblock && io.mem.acquire.ready, tlDataBeats)
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