fix TL width adapter and make it easier to switch inner data width
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a809a1712a
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@ -105,6 +105,8 @@ class BaseConfig extends Config (
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res append '\u0000'
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res.toString.getBytes
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}
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lazy val innerDataBits = site(MIFDataBits)
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lazy val innerDataBeats = (8 * site(CacheBlockBytes)) / innerDataBits
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pname match {
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case HtifKey => HtifParameters(
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width = Dump("HTIF_WIDTH", 16),
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@ -262,7 +264,7 @@ class BaseConfig extends Config (
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if (site(BuildRoCC).isEmpty) 1 else site(RoccMaxTaggedMemXacts)),
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maxClientsPerPort = if (site(BuildRoCC).isEmpty) 1 else 2,
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maxManagerXacts = site(NAcquireTransactors) + 2,
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dataBeats = site(MIFDataBeats),
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dataBeats = innerDataBeats,
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dataBits = site(CacheBlockBytes)*8)
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case TLKey("L2toMC") =>
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TileLinkParameters(
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@ -274,7 +276,7 @@ class BaseConfig extends Config (
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maxClientXacts = 1,
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maxClientsPerPort = site(NAcquireTransactors) + 2,
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maxManagerXacts = 1,
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dataBeats = site(MIFDataBeats),
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dataBeats = innerDataBeats,
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dataBits = site(CacheBlockBytes)*8)
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case TLKey("Outermost") => site(TLKey("L2toMC")).copy(
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maxClientXacts = site(NAcquireTransactors) + 2,
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@ -290,7 +292,7 @@ class BaseConfig extends Config (
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maxClientXacts = 4,
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maxClientsPerPort = 1,
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maxManagerXacts = 1,
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dataBeats = site(MIFDataBeats),
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dataBeats = innerDataBeats,
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dataBits = site(CacheBlockBytes) * 8)
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}
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case TLKey("MMIO_Outermost") => site(TLKey("L2toMMIO")).copy(dataBeats = site(MIFDataBeats))
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2
uncore
2
uncore
@ -1 +1 @@
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Subproject commit 9298f4239ce9d94caf46fa09f997cdb8b2bfbf84
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Subproject commit 2929d5384c54549d9af529643d2d4d61f9df626f
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