Set badaddr on breakpoints
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4cd77cef10
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@ -118,6 +118,7 @@ class CSRFileIO(implicit p: Parameters) extends CoreBundle {
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val custom_mrw_csrs = Vec(nCustomMrwCsrs, UInt(INPUT, xLen))
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val cause = UInt(INPUT, xLen)
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val pc = UInt(INPUT, vaddrBitsExtended)
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val badaddr = UInt(INPUT, vaddrBitsExtended)
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val fatc = Bool(OUTPUT)
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val time = UInt(OUTPUT, xLen)
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val fcsr_rm = Bits(OUTPUT, FPConstants.RM_SZ)
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@ -365,7 +366,7 @@ class CSRFile(implicit p: Parameters) extends CoreModule()(p)
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Mux[UInt](insn_break, Causes.breakpoint, Causes.illegal_instruction)))
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val cause_lsbs = cause(log2Up(xLen)-1,0)
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val causeIsDebugInt = cause(xLen-1) && cause_lsbs === debugIntCause
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val causeIsDebugBreak = insn_break && Cat(reg_dcsr.ebreakm, reg_dcsr.ebreakh, reg_dcsr.ebreaks, reg_dcsr.ebreaku)(reg_mstatus.prv)
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val causeIsDebugBreak = cause === Causes.breakpoint && Cat(reg_dcsr.ebreakm, reg_dcsr.ebreakh, reg_dcsr.ebreaks, reg_dcsr.ebreaku)(reg_mstatus.prv)
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val trapToDebug = Bool(usingDebug) && (causeIsDebugInt || causeIsDebugBreak || reg_debug)
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val delegate = Bool(p(UseVM)) && reg_mstatus.prv < PRV.M && Mux(cause(xLen-1), reg_mideleg(cause_lsbs), reg_medeleg(cause_lsbs))
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val debugTVec = Mux(reg_debug, UInt(0x808), UInt(0x800))
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@ -383,17 +384,6 @@ class CSRFile(implicit p: Parameters) extends CoreModule()(p)
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io.status.sd_rv32 := io.status.sd
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when (io.exception || csr_xcpt) {
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def compressVAddr(addr: UInt) =
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if (vaddrBitsExtended == vaddrBits) addr
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else {
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val (upper, lower) = Split(addr, vaddrBits)
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val sign = Mux(lower.toSInt < SInt(0), upper.andR, upper.orR)
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Cat(sign, lower)
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}
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val ldst =
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cause === Causes.fault_load || cause === Causes.misaligned_load ||
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cause === Causes.fault_store || cause === Causes.misaligned_store
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val badaddr = Mux(ldst, compressVAddr(io.rw.wdata), io.pc)
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val epc = ~(~io.pc | (coreInstBytes-1))
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val pie = read_mstatus(reg_mstatus.prv)
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@ -405,7 +395,7 @@ class CSRFile(implicit p: Parameters) extends CoreModule()(p)
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}.elsewhen (delegate) {
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reg_sepc := epc
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reg_scause := cause
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reg_sbadaddr := badaddr
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reg_sbadaddr := io.badaddr
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reg_mstatus.spie := pie
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reg_mstatus.spp := reg_mstatus.prv
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reg_mstatus.sie := false
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@ -413,7 +403,7 @@ class CSRFile(implicit p: Parameters) extends CoreModule()(p)
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}.otherwise {
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reg_mepc := epc
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reg_mcause := cause
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reg_mbadaddr := badaddr
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reg_mbadaddr := io.badaddr
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reg_mstatus.mpie := pie
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reg_mstatus.mpp := reg_mstatus.prv
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reg_mstatus.mie := false
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@ -171,6 +171,7 @@ class Rocket(implicit p: Parameters) extends CoreModule()(p) {
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val wb_reg_valid = Reg(Bool())
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val wb_reg_xcpt = Reg(Bool())
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val wb_reg_mem_xcpt = Reg(Bool())
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val wb_reg_replay = Reg(Bool())
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val wb_reg_cause = Reg(UInt())
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val wb_reg_rocc_pending = Reg(init=Bool(false))
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@ -369,15 +370,18 @@ class Rocket(implicit p: Parameters) extends CoreModule()(p) {
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}
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}
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val (mem_new_xcpt, mem_new_cause) = checkExceptions(List(
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(mem_reg_load && bpu.io.xcpt_ld, UInt(Causes.breakpoint)),
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(mem_reg_store && bpu.io.xcpt_st, UInt(Causes.breakpoint)),
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(want_take_pc_mem && mem_npc_misaligned, UInt(Causes.misaligned_fetch)),
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(mem_ctrl.mem && io.dmem.xcpt.ma.st, UInt(Causes.misaligned_store)),
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(mem_ctrl.mem && io.dmem.xcpt.ma.ld, UInt(Causes.misaligned_load)),
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(mem_ctrl.mem && io.dmem.xcpt.pf.st, UInt(Causes.fault_store)),
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(mem_ctrl.mem && io.dmem.xcpt.pf.ld, UInt(Causes.fault_load))))
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val (mem_xcpt, mem_cause) = checkExceptions(List(
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(mem_reg_xcpt_interrupt || mem_reg_xcpt, mem_reg_cause),
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(mem_reg_valid && mem_reg_load && bpu.io.xcpt_ld, UInt(Causes.breakpoint)),
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(mem_reg_valid && mem_reg_store && bpu.io.xcpt_st, UInt(Causes.breakpoint)),
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(want_take_pc_mem && mem_npc_misaligned, UInt(Causes.misaligned_fetch)),
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(mem_reg_valid && mem_ctrl.mem && io.dmem.xcpt.ma.st, UInt(Causes.misaligned_store)),
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(mem_reg_valid && mem_ctrl.mem && io.dmem.xcpt.ma.ld, UInt(Causes.misaligned_load)),
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(mem_reg_valid && mem_ctrl.mem && io.dmem.xcpt.pf.st, UInt(Causes.fault_store)),
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(mem_reg_valid && mem_ctrl.mem && io.dmem.xcpt.pf.ld, UInt(Causes.fault_load))))
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(mem_reg_xcpt_interrupt || mem_reg_xcpt, mem_reg_cause),
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(mem_reg_valid && mem_new_xcpt, mem_new_cause)))
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val dcache_kill_mem = mem_reg_valid && mem_ctrl.wxd && io.dmem.replay_next // structural hazard on writeback port
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val fpu_kill_mem = mem_reg_valid && mem_ctrl.fp && io.fpu.nack_mem
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@ -390,6 +394,7 @@ class Rocket(implicit p: Parameters) extends CoreModule()(p) {
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wb_reg_valid := !ctrl_killm
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wb_reg_replay := replay_mem && !take_pc_wb
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wb_reg_xcpt := mem_xcpt && !take_pc_wb
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wb_reg_mem_xcpt := mem_reg_valid && mem_new_xcpt && !(mem_reg_xcpt_interrupt || mem_reg_xcpt)
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when (mem_xcpt) { wb_reg_cause := mem_cause }
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when (mem_reg_valid || mem_reg_replay || mem_reg_xcpt_interrupt) {
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wb_ctrl := mem_ctrl
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@ -459,6 +464,7 @@ class Rocket(implicit p: Parameters) extends CoreModule()(p) {
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io.rocc.csr <> csr.io.rocc.csr
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csr.io.rocc.interrupt <> io.rocc.interrupt
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csr.io.pc := wb_reg_pc
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csr.io.badaddr := Mux(wb_reg_mem_xcpt, encodeVirtualAddress(wb_reg_wdata, wb_reg_wdata), wb_reg_pc)
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csr.io.uarch_counters.foreach(_ := Bool(false))
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io.ptw.ptbr := csr.io.ptbr
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io.ptw.invalidate := csr.io.fatc
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@ -625,7 +631,7 @@ class Rocket(implicit p: Parameters) extends CoreModule()(p) {
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def checkHazards(targets: Seq[(Bool, UInt)], cond: UInt => Bool) =
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targets.map(h => h._1 && cond(h._2)).reduce(_||_)
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def encodeVirtualAddress(a0: UInt, ea: UInt) = if (xLen == 32) ea else {
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def encodeVirtualAddress(a0: UInt, ea: UInt) = if (vaddrBitsExtended == vaddrBits) ea else {
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// efficient means to compress 64-bit VA into vaddrBits+1 bits
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// (VA is bad if VA(vaddrBits) != VA(vaddrBits-1))
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val a = a0 >> vaddrBits-1
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