riscv/rocket-chip
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Make dcsr.halt writable

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This commit is contained in:
Andrew Waterman 2016-06-09 12:29:26 -07:00
parent 8516e38eb2
commit 4cd77cef10
1 changed files with 1 additions and 0 deletions
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rocket/src/main/scala/csr.scala
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@ -501,6 +501,7 @@ class CSRFile(implicit p: Parameters) extends CoreModule()(p)
if (usingDebug) {
when (decoded_addr(CSRs.dcsr)) {
val new_dcsr = new DCSR().fromBits(wdata)
reg_dcsr.halt := new_dcsr.halt
reg_dcsr.ebreakm := new_dcsr.ebreakm
if (usingVM) reg_dcsr.ebreaks := new_dcsr.ebreaks
if (usingUser) reg_dcsr.ebreaku := new_dcsr.ebreaku