add a regression test for no-alloc Put following an alloc Put
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@ -166,6 +166,63 @@ class NoAllocPutHitRegression(implicit p: Parameters) extends Regression()(p) {
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io.cache.req.valid := Bool(false)
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}
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/** Make sure L2 does the right thing when multiple puts are sent for the
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* same block, but only the first one has the alloc bit set. */
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class MixedAllocPutRegression(implicit p: Parameters) extends Regression()(p) {
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val (s_idle :: s_put_send :: s_put_wait ::
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s_get_send :: s_get_wait :: s_done :: Nil) = Enum(Bits(), 6)
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val state = Reg(init = s_idle)
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val put_data = Vec(
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UInt("h0000000011111111"),
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UInt("h2222222200000000"),
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UInt("h3333333333333333"))
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val put_wmask = Vec(UInt("h0f"), UInt("hf0"), UInt("hff"))
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val put_beat = Vec(UInt(0), UInt(0), UInt(2))
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val (put_acq_id, put_acq_done) = Counter(
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state === s_put_send && io.mem.acquire.ready, 3)
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val (put_gnt_cnt, put_gnt_done) = Counter(
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state === s_put_wait && io.mem.grant.valid, 3)
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val get_data = Vec(UInt("h2222222211111111"), UInt("h3333333333333333"))
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val get_beat = Vec(UInt(0), UInt(2))
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val (get_acq_id, get_acq_done) = Counter(
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state === s_get_send && io.mem.acquire.ready, 2)
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val (get_gnt_cnt, get_gnt_done) = Counter(
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state === s_get_wait && io.mem.grant.valid, 2)
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val put_acquire = Put(
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client_xact_id = put_acq_id,
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addr_block = UInt(memStartBlock),
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addr_beat = put_beat(put_acq_id),
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data = put_data(put_acq_id),
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wmask = put_wmask(put_acq_id),
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alloc = (put_acq_id === UInt(0)))
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val get_acquire = Get(
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client_xact_id = get_acq_id,
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addr_block = UInt(memStartBlock),
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addr_beat = get_beat(get_acq_id))
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io.mem.acquire.valid := (state === s_put_send) || (state === s_get_send)
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io.mem.acquire.bits := Mux(state === s_put_send, put_acquire, get_acquire)
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io.mem.grant.ready := (state === s_put_wait) || (state === s_get_wait)
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when (state === s_idle && io.start) { state := s_put_send }
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when (put_acq_done) { state := s_put_wait }
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when (put_gnt_done) { state := s_get_send }
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when (get_acq_done) { state := s_get_wait }
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when (get_gnt_done) { state := s_done }
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io.finished := (state === s_done)
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assert(state =/= s_get_wait || !io.mem.grant.valid ||
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io.mem.grant.bits.data === get_data(io.mem.grant.bits.client_xact_id),
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"MixedAllocPutRegression: data mismatch")
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}
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/* Make sure each no-alloc put triggers a request to outer memory.
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* Unfortunately, there's no way to verify that this works except by looking
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* at the waveform */
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@ -426,7 +483,8 @@ object RegressionTests {
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Module(new PrefetchHitRegression),
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Module(new SequentialSameIdGetRegression),
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Module(new WritebackRegression),
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Module(new PutBeforePutBlockRegression))
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Module(new PutBeforePutBlockRegression),
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Module(new MixedAllocPutRegression))
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def broadcastRegressions(implicit p: Parameters) = Seq(
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Module(new IOGetAfterPutBlockRegression),
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Module(new WriteMaskedPutBlockRegression),
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