add BRAMSlave unittest
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377de06b72
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@ -592,6 +592,80 @@ class AtosConverterTest(implicit p: Parameters) extends UnitTest {
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io.finished := frontend.io.finished && backend.io.finished
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}
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class BRAMSlaveDriver(implicit val p: Parameters) extends Module
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with HasTileLinkParameters {
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val io = new Bundle {
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val mem = new ClientUncachedTileLinkIO
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val start = Bool(INPUT)
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val finished = Bool(OUTPUT)
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}
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val (s_idle :: s_pf_req :: s_pf_stall :: s_pf_resp ::
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s_put_req :: s_put_stall :: s_put_resp ::
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s_get_req :: s_get_stall :: s_get_resp ::
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s_done :: Nil) = Enum(Bits(), 11)
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val state = Reg(init = s_idle)
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val pf_acquire = PutPrefetch(
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client_xact_id = UInt(0),
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addr_block = UInt(0))
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val (put_beat, put_done) = Counter(
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state === s_put_req && io.mem.acquire.ready, tlDataBeats)
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val put_data = Fill(tlDataBits / tlBeatAddrBits, put_beat)
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val put_acquire = PutBlock(
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client_xact_id = UInt(0),
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addr_block = UInt(0),
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addr_beat = put_beat,
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data = put_data)
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val get_acquire = GetBlock(
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client_xact_id = UInt(0),
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addr_block = UInt(0))
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val (get_beat, get_done) = Counter(
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state === s_get_resp && io.mem.grant.valid, tlDataBeats)
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val get_data = Fill(tlDataBits / tlBeatAddrBits, get_beat)
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val (stall_cnt, stall_done) = Counter(
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state === s_pf_stall || state === s_put_stall || state === s_get_stall, 4)
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io.mem.acquire.valid := (state === s_pf_req) || (state === s_put_req) || (state === s_get_req)
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io.mem.acquire.bits := MuxBundle(state, get_acquire, Seq(
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s_pf_req -> pf_acquire,
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s_put_req -> put_acquire))
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io.mem.grant.ready := (state === s_pf_resp) || (state === s_put_resp) || (state === s_get_resp)
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when (state === s_idle && io.start) { state := s_pf_req }
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when (state === s_pf_req && io.mem.acquire.ready) { state := s_pf_stall }
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when (state === s_pf_stall && stall_done) { state := s_pf_resp }
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when (state === s_pf_resp && io.mem.grant.valid) { state := s_put_req }
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when (state === s_put_req && io.mem.acquire.ready) { state := s_put_stall }
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when (state === s_put_stall && stall_done) { state := s_put_req }
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when (put_done) { state := s_put_resp }
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when (state === s_put_resp && io.mem.grant.valid) { state := s_get_req }
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when (state === s_get_req && io.mem.acquire.ready) { state := s_get_stall }
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when (state === s_get_stall && stall_done) { state := s_get_resp }
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when (state === s_get_resp && io.mem.grant.valid) { state := s_get_stall }
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when (get_done) { state := s_done }
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io.finished := (state === s_done)
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assert(!io.mem.grant.valid || !io.mem.grant.bits.hasData() ||
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io.mem.grant.bits.data === get_data,
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"BRAMSlaveTest: data doesn't match")
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}
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class BRAMSlaveTest(implicit val p: Parameters) extends UnitTest
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with HasTileLinkParameters {
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val driver = Module(new BRAMSlaveDriver)
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val bram = Module(new BRAMSlave(tlDataBeats))
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driver.io.start := io.start
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io.finished := driver.io.finished
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bram.io <> driver.io.mem
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}
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class UnitTestSuite(implicit p: Parameters) extends GroundTest()(p) {
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val tests = Seq(
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Module(new MultiWidthFifoTest),
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@ -599,7 +673,8 @@ class UnitTestSuite(implicit p: Parameters) extends GroundTest()(p) {
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Module(new TileLinkToSmiConverterTest),
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Module(new AtosConverterTest),
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Module(new NastiMemoryDemuxTest),
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Module(new HastiTest))
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Module(new HastiTest),
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Module(new BRAMSlaveTest))
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val s_idle :: s_start :: s_wait :: Nil = Enum(Bits(), 3)
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val state = Reg(init = s_idle)
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@ -607,6 +682,10 @@ class UnitTestSuite(implicit p: Parameters) extends GroundTest()(p) {
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when (state === s_idle) { state := s_start }
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when (state === s_start) { state := s_wait }
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tests.foreach { mod => mod.io.start := (state === s_start) }
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tests.zipWithIndex.foreach { case (mod, i) =>
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mod.io.start := (state === s_start)
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val timeout = Timer(1000, mod.io.start, mod.io.finished)
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assert(!timeout, s"UnitTest $i timed out")
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}
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io.finished := tests.map(_.io.finished).reduce(_ && _)
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}
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