riscv/rocket-chip
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make sure SlowIO clock divider is initialized on reset

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This commit is contained in:
Howard Mao 2016-06-08 10:02:21 -07:00
parent 28161cab45
commit 636a46c052
1 changed files with 2 additions and 2 deletions
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4
junctions/src/main/scala/slowio.scala
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@ -26,8 +26,8 @@ class SlowIO[T <: Data](val divisor_max: Int)(data: => T) extends Module
}
io.divisor := (hold << 16) | divisor
val count = Reg{UInt(width = log2Up(divisor_max))}
val myclock = Reg{Bool()}
val count = Reg(init = UInt(0, log2Up(divisor_max)))
val myclock = Reg(init = Bool(false))
count := count + UInt(1)
val rising = count === (divisor >> 1)